MT28F004B3VG-8 T TR Micron Technology Inc, MT28F004B3VG-8 T TR Datasheet - Page 8

IC FLASH 4MBIT 80NS 40TSOP

MT28F004B3VG-8 T TR

Manufacturer Part Number
MT28F004B3VG-8 T TR
Description
IC FLASH 4MBIT 80NS 40TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT28F004B3VG-8 T TR

Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
4M (512K x 8)
Speed
80ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
40-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
task and when an ERASE has been suspended. Addi-
tional error information is set in three other bits: V
status, write status and erase status.
Command Execution Logic (CEL)
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register
or status register). Commands may be issued to the
CEL while the ISM is active. However, there are restric-
tions on .what commands are allowed in this condi-
tion. See the Command Execution section for more
detail.
Deep Power-Down Mode
MT28F004B3 and MT28F400B3 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to V
draw is a maximum of 8µA at 3.3V V
power-down also clears the status register and sets the
ISM to the read array mode.
Memory Architecture
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into seven addressable blocks that vary in size
and are independently erasable. When blocks rather
than the entire array are erased, total device endur-
09005aef8114a789
F45.fm - Rev. E 6/04 EN
The CEL receives and interprets commands to the
To allow for maximum power conservation, the
The MT28F004B3 and MT28F400B3 memory array
WORD ADDRESS
SS
30000h
20000h
10000h
04000h
03000h
02000h
00000h
03FFFh
02FFFh
01FFFh
±0.2V. In this mode, the current
3FFFFh
2FFFFh
1FFFFh
0FFFFh
MT28F004B3/400B3xx-xxB
BYTE ADDRESS
Bottom Boot
60000h
40000h
20000h
08000h
06000h
04000h
00000h
7FFFFh
5FFFFh
3FFFFh
1FFFFh
07FFFh
05FFFh
03FFFh
Figure 3: Memory Address Maps
CC
8KB Parameter Block
8KB Parameter Block
. Entering deep
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
SMART 3 BOOT BLOCK FLASH MEMORY
PP
8
ance is enhanced, as is system flexibility. Only the
ERASE function is block-oriented. All READ and
WRITE operations are done on a random-access basis.
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage (V
to RP# or that the WP# pin be driven HIGH before era-
sure is commenced. The boot block is intended for the
core firmware required for basic system functionality.
The remaining six blocks do not require either of these
two conditions be met before WRITE or ERASE opera-
tions.
Boot Block
ware. This 16KB block may only be erased or written
when the RP# pin is at the specified boot block
unlock voltage (V
V
RP# pin must be held at V
HIGH until the ERASE or WRITE is completed. The
V
block is written to or erased.
in two configurations and top or bottom boot block.
The top boot block version supports processors of the
x86 variety. The bottom boot block version is
intended for 680X0 and RISC applications. Figure 1
illustrates the memory address maps associated with
these two versions.
WORD ADDRESS
IH
PP
The boot block is protected from unintentional
The hardware-protected boot block provides extra
security for the most sensitive portions of the firm-
The MT28F004B3 and MT28F400B3 are available
3D000h
3E000h
3DFFFh
3C000h
30000h
20000h
10000h
00000h
3CFFFh
3BFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
. During a WRITE or ERASE of the boot block, the
pin must be at V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F004B3/400B3xx-xxT
BYTE ADDRESS
7A000h
7C000h
78000h
60000h
40000h
20000h
00000h
7BFFFh
7FFFFh
79FFFh
77FFFh
5FFFFh
3FFFFh
1FFFFh
Top Boot
HH
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
) of 12V or when the WP# pin is
PPH
(3.3V or 5V ) when the boot
©2003 Micron Technology, Inc. All rights reserved.
HH
or the WP# pin held
HH
) be applied
4Mb

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