MT28F800B3SG-9 BET

... ONLY, DUAL SUPPLY (SMART 3) 40-Pin TSOP Type I GENERAL DESCRIPTION The MT28F008B3 (x8) and MT28F800B3 (x16/x8) Marking are low-voltage, nonvolatile, electrically block-eras- able (flash), programmable memory devices contain- -9 ing 8,388,608 bits organized as 524,288 words (16 bits) or 1,048,576 bytes (8 bits). Writing and erasing the MT28F008B3 MT28F800B3 device is done with a V while all operations are performed with a 3 ...

... DQ12 38 DQ4 DQ11 35 DQ3 34 DQ10 33 DQ2 32 DQ9 31 DQ1 30 DQ8 29 DQ0 ORDER NUMBER AND PART MARKING MT28F800B3SG-9 B MT28F800B3SG-9 T MT28F800B3SG-9 BET MT28F800B3SP-9 BET MT28F800B3SG-9 TET MT28F800B3SP-9 TET 40-Pin TSOP Type I A16 1 40 A15 2 39 A14 3 38 A13 4 37 A12 5 36 A11 WE RP ...

... Control 1 WP# CE# Command OE# Execution WE# Logic RP NOTE: 1. Does not apply to MT28F800B3SG. 2. Does not apply to MT28F008B3. Figure 2: Functional Block Diagran 16KB Boot Block 8KB Parameter Block 19 (20) 10 8KB Parameter Block 96KB Main Block 9 128KB Main Block (10) 128KB Main Block Addr. 128KB Main Block ...

... SMART 3 BOOT BLOCK FLASH MEMORY SYMBOL TYPE WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL the memory array. WP# Input Write Protect: Unlocks the boot block when HIGH (3.3V PPH ERASE ...

... The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP RP# may 12V 12V; may also be read by issuing the IDENTIFY DEVICE command A1–A8, A10–A18 = 10. Value reflects DQ8–DQ15. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 CE# OE# WE# WP# BYTE ...

... Operation must be preceded by WRITE SETUP command. 5. The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP RP# may 12V 12V; may also be read by issuing the IDENTIFY DEVICE command A1–A8, A10–A19 = 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 RP# CE# OE# WE ...

... The MT28F800B3 allows selection of an 8-bit (1 Meg 16-bit (512K x 16) data bus for reading and writ- ing the memory. The BYTE# pin is used to select the bus width. In the x16 configuration, control data is read or written only on the lower eight bits (DQ0– ...

... Command Execution Logic (CEL) The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, ID register or status register). Commands may be issued to the CEL while the ISM is active. However, there are restric- tions on what commands are allowed in this condition ...

... The MT28F800B3 features selectable bus widths. When the memory array is accessed as a 512K x 16, BYTE# is HIGH, and data is output on DQ0–DQ15. To access the memory array Meg x 8, BYTE# must be LOW, DQ8–DQ14 must be High-Z, and all data must be output on DQ0–DQ7. The DQ15/(A-1) pin becomes the lowest order address input so that 1,048,576 loca- tions can be read ...

... CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the device. A WRITE is used to input data to the memory array. The following sec- tion describes both types of inputs. More information describing how to use the two types of inputs to write or erase the device is provided in the Command Execu- tion section ...

... SR0–2 RESERVED 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY All of the defined bits are set by the ISM, but only the ISM and erase suspend status bits are reset by the ISM. The erase, write and V cleared using CLEAR STATUS REGISTER. If the V ...

... Addresses are “Don’t Care” in first cycle but must be held stable Address to be written Data to be written to WA. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY the write address and data are issued and V brought to V requires that the RP# pin be brought to V ...

... NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY ERASE Suspension The only command that may be issued while an ERASE is in progress is ERASE SUSPEND. This com- mand enables other commands to be executed while pausing the ERASE in progress ...

... ISM continues to operate, and the device consumes the respective active power until the WRITE or ERASE is completed. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Power-Up The likelihood of unwanted WRITE or ERASE opera- tions is minimized because two consecutive cycles are required to execute either operation. However, to reset ...

... If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 Start (WRITE completed Micron Technology, Inc ...

... If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 8: Complete BLOCK ERASE 1 Start (ERASE completed) NO ...

... Figure 9: ERASE SUSPEND/RESUME SEQUENCE 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Start (ERASE in progress) WRITE B0h (ERASE SUSPEND 3. STATUS REGISTER READ NO SR7 = 1? YES NO SR6 = 1? YES WRITE FFh (READ ARRAY) Done NO Reading? YES WRITE D0h (ERASE RESUME) Resume ERASE 17 ERASE Completed Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

... All voltages referenced 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied ...

... NOTE: 1. Vcc = MAX Vcc during I tests dependent on cycle rates dependent on output loading. Specified values are obtained with the outputs open. CC 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY SYMBOL 1 ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL SUPPLY SUPPLY 19 MAX ...

... Input pulse levels Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . .<10ns Input timing reference level . . . . . . . . . . . . . . . . . . . . 1.5V Output timing reference level 1.5V Output load 1TTL gate and CL = 50pF 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL ...

... Extended Temperature (-40ºC ≤ -9/-9 ET SYMBOL MIN MAX ACE t AOE t AA NOTE: 1. BYTE# = HIGH (MT28F800B3 only). 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 10: Word-Wide READ Cycle VALID ADDRESS ACE t AOE ≤ +70ºC) ≤ +85ºC) UNITS SYMBOL t ns RWH ...

... A -9/-9 ET SYMBOL MIN MAX ACE t AOE t AA NOTE: 1. BYTE# = LOW (MT28F800B3 only). 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 11: Byte-Wide READ Cycle VALID ADDRESS ACE t AOE HIGH-Z t RWH ≤ +70°C) ≤ +85°C) UNITS SYMBOL t ns RWH t 90 ...

... Applies to MT28F008B3 and MT28F800B3 with BYTE# = LOW. 7. Parameter is specified when device is not accessed. Actual current draw will be I executed while the device is in erase suspend mode. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL V PPLK ...

... WRITE or ERASE to boot block. 7. Typical values measured +25º Assumes no system overhead. 9. Typical WRITE times use checkerboard data pattern. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL WPH ( ...

... Address inputs are “Don’t Care” but must be held stable BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit. 3. Either RP WP# HIGH unlocks the boot block. HH 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 12: WRITE/ERASE Cycle WE#-Controlled WRITE/ERASE Note ...

... Address inputs are “Don’t Care” but must be held stable BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit. 3. Either RP WP# HIGH unlocks the boot block. HH 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 13: WRITE/ERASE Cycle CE#-Controlled WRITE/ERASE Note ...

... NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 14: 40-Pin Plastic TSOP I (10mm x 20mm) 0.25 FOR REFERENCE ONLY 1.20 MAX SEE DETAIL A Micron Technology, Inc ...

... NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 15: 48-Pin Plastic TSOP I (12mm x 20mm) 20.00 ±0.25 18.40 ±0.08 SEE DETAIL A 1 ...

... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 16: 44-Pin Plastic SOP1 (500 mil) +0.05 0.45 (TYP) -0 ...

... MT28F008B3 only available in VG package • Added 80ns access time for commercial and extended temperature ranges 09005aef81136a91 Q10.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. 30 8Mb ©2001 Micron Technology, Inc. All rights reserved. ...