IC FLASH 8MBIT 90NS 44SOP

 

MT28F800B3SG-9 BET TR

Manufacturer Part NumberMT28F800B3SG-9 BET TR
DescriptionIC FLASH 8MBIT 90NS 44SOP
ManufacturerMicron Technology Inc
MT28F800B3SG-9 BET TR datasheets

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Specifications of MT28F800B3SG-9 BET TR

Format - MemoryFLASHMemory TypeFLASH - Nor
Memory Size8M (1M x 8 or 512K x 16)Speed90ns
InterfaceParallelVoltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CPackage / Case44-SOP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Input Operations
The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control
the mode of operation of the device. A WRITE is used
to input data to the memory array. The following sec-
tion describes both types of inputs. More information
describing how to use the two types of inputs to write
or erase the device is provided in the Command Execu-
tion section.
Commands
To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit
command is input on DQ0–DQ7, while DQ8–DQ15 are
“Don’t Care” on the MT28F800B3. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# on the MT28F800B3 has no effect
on a command input.
Memory Array
A WRITE to the memory array sets the desired bits
to logic 0s but cannot change a given bit to a logic 1
from a logic 0. Setting any bits to a logic 1 requires that
the entire block be erased. To perform a WRITE, OE#
Table 4:
Command Set
COMMAND
HEX CODE
RESERVED
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP
ERASE CONFIRM/RESUME
WRITE SETUP
40h or 10h
ERASE SUSPEND
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
SMART 3 BOOT BLOCK FLASH MEMORY
must be HIGH, CE# and WE# must be LOW, and V
must be set to V
block also requires that the RP# pin be at V
be HIGH. A0–A18 (A19) provide the address to be writ-
ten, while the data to be written to the array is input on
the DQ pins. The data and addresses are latched on the
rising edge of CE# (CE#-controlled) or WE# (WE#-con-
trolled), whichever occurs first. A WRITE must be pre-
ceded by a WRITE SETUP command. Details on how to
input data to the array are described in the Write
Sequence section.
Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F800B3. When BYTE# is LOW (byte
mode), data is input on DQ0–DQ7, DQ8–DQ14 are
High-Z, and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is
input on DQ0–DQ15.
Command Set
To simplify writing of the memory blocks, the
MT28F800B3 and MT28F008B3 incorporate an ISM
that controls all internal algorithms for writing and
erasing the floating gate memory cells. An 8-bit com-
mand set is used to control the device. Details on how
to sequence commands are provided in the Command
Execution section. Table 4 lists the valid commands.
DESCRIPTION
00h
This command and all unlisted commands are invalid and should not be
called. These commands are reserved to allow for future feature
enhancements.
FFh
Must be issued after any other command cycle before the array can be
read. It is not necessary to issue this command after power-up or RESET.
90h
Allows the device and manufacturer compatibility ID to be read. A0 is used
to decode between the manufacturer compatibility ID (A0 = LOW) and
device ID (A0 = HIGH).
70h
Allows the status register to be read. Please refer to Table 5 for more
information on the status register bits.
50h
Clears status register bits 3-5, which cannot be cleared by the ISM.
20h
The first command given in the two-cycle ERASE sequence. The ERASE is
not completed unless followed by ERASE CONFIRM.
D0h
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND
to resume the ERASE.
The first command given in the two-cycle WRITE sequence. The write data
and address are given in the following cycle to complete the WRITE.
B0h
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER, READ
ARRAY and ERASE RESUME commands may be executed.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
8Mb
1 or V
2. Writing to the boot
PPH
PPH
or WP#
HH
©2001 Micron Technology, Inc. All rights reserved.
PP

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