MT45W1MW16BAFB-706 WT Micron Technology Inc, MT45W1MW16BAFB-706 WT Datasheet - Page 11

• Manufacturer Part Number: MT45W1MW16BAFB-706 WT
• Description: IC PSRAM 16MBIT 70NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-706 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 7:
Burst Mode Operation
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
Page Mode READ Operation (ADV = LOW)
ADDRESS
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consist of a multi-clock sequence that must be performed in an
ordered fashion. After CE# goes LOW, the address to access is latched on the next rising
edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether
the operation is going to be a READ (WE# = HIGH, Figure 8 on page 12) or WRITE (WE#
= LOW, Figure 9 on page 12).
The size of a burst can be specified in the BCR as either fixed-length or continuous.
Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the
ability to start at a specified address and burst through the entire memory. The latency
count stored in the BCR defines the number of clock cycles that elapse before the initial
data value is transferred between the processor and CellularRAM device.
The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to
indicate when data is to be transferred into (or out of ) the memory. WAIT will again be
asserted if the burst crosses the boundary between 128-word rows. Once the Cellular-
RAM device has restored the previous row’s data and accessed the next row, WAIT will be
de-asserted and the burst can continue (see Figure 35 on page 44).
The processor can access other devices without incurring the timing penalty of the ini-
tial latency for a new burst by suspending burst mode. Bursts are suspended by stopping
CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the
burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; oth-
erwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and
as a result, no other devices should directly share the WAIT connection to the controller.
To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data
is available on the bus.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
will cause CE# to remain LOW for longer than
burst restarted with a new CE# LOW/ADV# LOW cycle.
LB#/UB#
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
DATA
WE#
OE#
CE#
t
CEM unless row boundaries are crossed at least every
ADDRESS[0]
t AA
D[0]
ADDRESS
t APA
[1]
< t CEM
11
D[1]
ADDRESS
t APA
[2]
D[2]
ADDRESS
t APA
[3]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[3]
DON’T CARE
t
CEM, CE# should be taken HIGH and the
t
CEM. If a burst suspension
Bus Operating Modes
©2003 Micron Technology, Inc. All rights reserved.