MT45W1MW16BAFB-708 WT Micron Technology Inc, MT45W1MW16BAFB-708 WT Datasheet - Page 14

IC PSRAM 16MBIT 70NS 54FBGA

MT45W1MW16BAFB-708 WT

Manufacturer Part Number
MT45W1MW16BAFB-708 WT
Description
IC PSRAM 16MBIT 70NS 54FBGA
Manufacturer
Micron Technology Inc

Specifications of MT45W1MW16BAFB-708 WT

Format - Memory
RAM
Memory Type
PSRAM (Page)
Memory Size
16M (1M x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-30°C ~ 85°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 11:
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
DQ[15:0]
LB#/UB#
A[20:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Refresh Collision During READ Operation
Additional WAIT states inserted to allow refresh completion.
High-Z
Note:
ADDRESS
VALID
tions, any disabled bytes will not be transferred to the RAM array and the internal value
will remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT
asserted during delay.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[0]
D[1]
Bus Operating Modes
D[2]
UNDEFINED
©2003 Micron Technology, Inc. All rights reserved.
D[3]
DON’T CARE

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