MT45W1MW16BAFB-708 WT Micron Technology Inc, MT45W1MW16BAFB-708 WT Datasheet - Page 6

• Manufacturer Part Number: MT45W1MW16BAFB-708 WT
• Description: IC PSRAM 16MBIT 70NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-708 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1:
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
H6, G2, H1, D3,
G3, H5, H4, H3,
H2, D4, C4, C3,
B4, B3, A5, A4,
D2, C2, C1, B1,
E4, F4, F3, G4,
G1, F1, F2, E2,
G6, F6, F5, E5,
D5, C6, C5, B6
Assignment
E3, J4, J5, J6
VFBGA
A3
A6
A2
G5
A1
D6
D1
B5
B2
E1
E6
J2
J3
J1
VFBGA Ball Descriptions
DQ[15:0]
Symbol
A[20:0]
ADV#
WAIT
V
V
WE#
OE#
UB#
CLK
CRE
CE#
LB#
V
V
NC
CC
SS
CC
SS
Note:
Q
Q
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Output
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
The CLK and ADV# inputs can be tied to V
nous or page mode. WAIT will be asserted but should be ignored during asynchronous and
page mode operations.
–
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the bus configuration register
or the refresh configuration register. On the 16Mb device, A20 (ball H6) is not
internally connected.
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static LOW
during asynchronous access READ and WRITE operations and during PAGE READ
ACCESS operations.
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# can be held LOW during asynchronous READ and
WRITE operations.
Configuration Register Enable: When CRE is HIGH, WRITE operations load the
refresh configuration register or bus configuration register.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
Not internally connected.
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.
V
V
SS
SS
Q must be connected to ground.
must be connected to ground.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
Description
if the device is always operating in asynchro-
General Description
©2003 Micron Technology, Inc. All rights reserved.