MT45W1MW16BAFB-708 WT TR Micron Technology Inc, MT45W1MW16BAFB-708 WT TR Datasheet - Page 25

• Manufacturer Part Number: MT45W1MW16BAFB-708 WT TR
• Description: IC PSRAM 16MBIT 70NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Refresh Configuration Register
Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh
Figure 22:
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
RCR[19]
0
1
Refresh Configuration Register Mapping
Select RCR
Select BCR
RCR[7]
on the 32Mb device only.
Register Select
All must be set to "0"
0
1
RCR[6] RCR[5]
1
1
0
0
Page Mode Disabled (default)
Page Mode Enable
RESERVED
20
A20
Page Mode Enable/Disable
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce cur-
rent consumption during standby mode. Page mode control is also embedded into the
RCR. Figure 22 below describes the control bits used in the RCR. At power-up, the RCR is
set to 0010h.
The RCR is accessed using CRE and A[19] LOW or through the configuration register
software access sequence with DQ = 0000h on the third cycle (see “Configuration Regis-
ters” on page 16).
The PAR bits restrict refresh operation to a portion of the total memory array. This fea-
ture allows the device to reduce standby current by refreshing only that part of the mem-
ory array required by the host system. The refresh options are full array, one-half array,
one-quarter array, one-eighth array, or none of the array. The mapping of these parti-
tions can start at either the beginning or the end of the address map (see Table 6 and
Table 7 on page 26).
1
0
1
0
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Register
Select
+15˚C
+85˚C
Internal sensor (default)
+45˚C
Maximum Case Temp.
All must be set to "0"
19
A19
RESERVED
18–8
A[18:8]
PAGE
7
A7
6
TCR
A6
5
25
A5
RCR[4]
DPD
0
1
4
A4
Must be set to "0"
RESERVED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DPD Enable
DPD Disable (default)
3
A3
Deep Power-Down
RCR[2]
0
0
0
0
1
1
1
1
2
A2
RCR[1]
1
1
1
0
0
0
0
1
PAR
1
Configuration Registers
A1
RCR[0]
0
1
0
1
1
0
0
1
©2003 Micron Technology, Inc. All rights reserved.
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/8 array
Top 1/4 array
Full array (default)
Bottom 1/2 array
A0
0
Refresh Coverage
Read Configuration
Address Bus
Register