MT45W1MW16BAFB-708 WT TR Micron Technology Inc, MT45W1MW16BAFB-708 WT TR Datasheet - Page 5

• Manufacturer Part Number: MT45W1MW16BAFB-708 WT TR
• Description: IC PSRAM 16MBIT 70NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
Figure 2:
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
ADV#
WAIT
WE#
OE#
UB#
CLK
CRE
CE#
Functional Block Diagram – 2 Meg x 16 and 1 Meg x 16
LB#
(for 32Mb)
(for 16Mb)
A[20:0]
A[19:0]
Note:
Control
Logic
Micron
for low-power, portable applications. The MT45W2MW16BA is a 32Mb DRAM core
device organized as 2 Meg x 16 bits; the MT45W1MW16BA is a 16Mb DRAM core
device organized as 1 Meg x 16 bits. These devices include an industry-standard
burst mode Flash interface that dramatically increases read/write bandwidth compared
with other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a trans-
parent self-refresh mechanism. The hidden refresh requires no additional support from
the system memory controller and has no significant impact on device read/write per-
formance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM
array. These registers are automatically loaded with default settings during power-up
and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three system-accessible mechanisms to minimize
standby current. Partial array refresh (PAR) limits refresh to only that part of the DRAM
array that contains essential data. Temperature compensated refresh (TCR) uses an on-
chip sensor to adjust the refresh rate to match the device temperature. The refresh rate
decreases at lower temperatures to minimize current consumption during standby. TCR
can also be set by the system for maximum device temperatures of +85°C, +45°C, and
+15°C. Deep power-down (DPD) halts the REFRESH operation altogether and is used
when no vital information is stored in the device. These three refresh mechanisms are
accessed through the RCR.
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Functional block diagrams illustrate simplified device operation. See truth table, ball
descriptions, and timing diagrams for detailed information.
®
CellularRAM™ products are high-speed, CMOS PSRAM memories developed
Refresh Configuration
Bus Configuration
Address Decode
Register (RCR)
Register (BCR)
Logic
5
(1,024K x 16)
2,048K x 16
MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ARRAY
DRAM
Output
Buffers
Input/
MUX
and
General Description
©2003 Micron Technology, Inc. All rights reserved.
DQ[15:8]
DQ[7:0]