MT45W1MW16BAFB-708 WT TR Micron Technology Inc, MT45W1MW16BAFB-708 WT TR Datasheet - Page 59

• Manufacturer Part Number: MT45W1MW16BAFB-708 WT TR
• Description: IC PSRAM 16MBIT 70NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Revision History
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/05
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 01/05
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/04
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/04
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
• Added new 16Mb part-specific note.
• Added 16Mb device.
• Clarified data values in Figure 41 on page 50.
• Corrected typographic error.
• Removed 60ns and 104 MHz support.
• Clarified Note 1, clock state, on page 7.
• Added Table 10, Maximum Standby Currents for Applying PAR and TCR Settings –
• Added Table 11, Maximum Standby Currents for Applying PAR and TCR Settings –
• Added Figure 23, Typical Refresh Current vs. Temperature (I
• Added software access.
• CR WRITE diagram titles updated to reflect WRITEs followed by READ ARRAY opera-
• Added 80 MHz burst clock (-708).
• Changed PAR options to full, one-half, one-quarter, one-eighth, or none.
• Corrected Table 17 typo.
• Added Note 3 to Fig. 35 and 41.
• Added
• Clarified READ/WRITE operating currents.
• Added clarifying notes for required refresh opportunity for BCR[15], depending on
• Added ADV# timing parameters and
• Changed C
• Added C
• Clarified CE# LOW time limited by refresh—must not stay LOW longer than
• Added
• Changed
• Aligned
• Deleted Appendix A (extended timings and all references).
• Updated I
• Changed doc status to “preliminary.”
• Clarified burst latency at row-boundary crossings.
• Replaced abbreviated component marks with part numbering chart.
• Added measurement-time clarification to I
• Changed
• Corrected package nomenclature to VFBGA.
• Clarified address A[4] and higher for page mode.
• Clarified CRE in Figure 14.
• Updated
• Updated package diagram.
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
32Mb, on page 29.
32Mb Low-Power (L), on page 29.
tion.
BCR setting.
Operation descriptions and timing diagrams.
t
t
CO to Figure 47 and Table 47.
CEM to Asynchronous WRITE, Page Mode READ Operation, and Burst Mode
t
IN
ACLK,
t
t
t
KP to 4ns for the -108, and 5ns for the -706 and -856 parts.
CC
CEM MAX to 8.
CBPH to
IN
and C
values and symbols.
and C
t
KHTL,
IO
t
MIN values.
IO
CPH for async–async transitions.
MAX values to 6.5pF.
t
ABA, and
59
t
CSP with consortium values.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CO to Fig. 48 and Table 48.
SB
and I
PAR
notes.
TCR
©2003 Micron Technology, Inc. All rights reserved.
) – 32Mb, on page 30.
Revision History
t
CEM.