MT45W1MW16BAFB-708 WT TR Micron Technology Inc, MT45W1MW16BAFB-708 WT TR Datasheet - Page 9

IC PSRAM 16MBIT 70NS 54FBGA

MT45W1MW16BAFB-708 WT TR

Manufacturer Part Number
MT45W1MW16BAFB-708 WT TR
Description
IC PSRAM 16MBIT 70NS 54FBGA
Manufacturer
Micron Technology Inc

Specifications of MT45W1MW16BAFB-708 WT TR

Format - Memory
RAM
Memory Type
PSRAM (Page)
Memory Size
16M (1M x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-30°C ~ 85°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
Power-Up Initialization Timing
In general, the MT45W2MW16BA and MT45W1MW16BA devices are high-density alter-
natives to SRAM and Pseudo SRAM products popular in low-power, portable applications.
The MT45W2MW16BA contains a 33,554,432-bit DRAM core organized as 2,097,152
addresses by 16 bits. The MT45W1MW16BA contains a 16,777,216-bit DRAM core orga-
nized as 1,048,576 addresses by 16 bits. Both devices implement the same high-speed
bus interface found on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-
chronous read protocol.
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their default
settings (see Figure 17 on page 21 and Figure 22 on page 25). V
applied simultaneously. When they reach a stable level at or above 1.70V, the device will
require 150µs to complete its self-initialization process. During the initialization period,
CE# should remain HIGH. When initialization is complete, the device is ready for nor-
mal operation.
VccQ
The MT45W2MW16BA and MT45W1MW16BA CellularRAM products incorporate a
burst mode interface found on Flash products targeting low-power, wireless applica-
tions. This bus interface supports asynchronous, page mode, and burst mode read and
write transfers. The specific interface supported is defined by the value loaded into the
bus configuration register. Page mode is controlled by the refresh configuration register
(RCR[7]).
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry- standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE#
HIGH. Valid data will be driven out of the I/Os after the specified access time has
elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/UB# are driven
LOW. During asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE#
will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or
LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can
either use the ADV input to latch the address, or ADV can be driven LOW during the
entire READ/WRITE operation.
During asynchronous operation, the CLK input
driven while the device is enabled and its state should be ignored. WE# LOW time must
be limited to
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Vcc
Vcc = 1.70V
t
CEM.
Device Initialization
t PU > 150µs
9
Device ready for
normal operation
Micron Technology, Inc., reserves the right to change products or specifications without notice.
must
be held
Functional Description
static
CC
©2003 Micron Technology, Inc. All rights reserved.
and V
LOW. WAIT will be
CC
Q must be

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