MT45W1MW16BAFB-856 WT Micron Technology Inc, MT45W1MW16BAFB-856 WT Datasheet - Page 13

• Manufacturer Part Number: MT45W1MW16BAFB-856 WT
• Description: IC PSRAM 16MBIT 85NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-856 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Mixed-Mode Operation
WAIT Operation
Figure 10:
LB#/UB# Operation
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
Wired or WAIT Configuration
The device can support a combination of synchronous READ and asynchronous WRITE
operations when the BCR is configured for synchronous operation. The asynchronous
WRITE operation requires that the clock (CLK) remain LOW during the entire sequence.
The ADV# signal can be used to latch the target address, or it can remain LOW during the
entire WRITE operation. CE# must return HIGH when transitioning between mixed-
mode operations. Note that the
time is required to ensure adequate refresh. Mixed-mode operation facilitates a seam-
less interface to legacy burst mode Flash memory controllers. See Figure 43 on page 52
for the “Asynchronous WRITE Followed by Burst READ” timing diagram.
The WAIT output on a CellularRAM device is typically connected to a shared, system-
level WAIT signal (see Figure 10 below). The shared WAIT signal is used by the processor
to coordinate transactions with multiple memories on the synchronous bus.
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that
the CellularRAM device requires additional time before data can be transferred. For
READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the
data burst will progress on successive clock edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration
BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data corruption. (Note
that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-asserts, and for
row boundary crossings, start one cycle after the WAIT signal asserts.)
The WAIT output also performs an arbitration role when a READ or WRITE operation is
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted
for additional clock cycles until the refresh has completed (see Figures 11 and 12 on
page 15). When the refresh operation has completed, the READ or WRITE operation will
continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary.
The WAIT assertion allows time for the new row to be accessed and permits any pending
refresh operations to be performed.
The LB# enable and UB# enable signals support byte-wide data transfers. During READ
operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a dis-
abled byte are put into a High-Z state during a READ operation. During WRITE opera-
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Processor
READY
WAIT
Device
Other
CellularRAM
WAIT
13
WAIT
Device
Other
t
CKA period is the same as a READ or WRITE cycle. This
Micron Technology, Inc., reserves the right to change products or specifications without notice.
External
Pull-Up/
Pull-Down
Resistor
Bus Operating Modes
©2003 Micron Technology, Inc. All rights reserved.