MT45W1MW16BAFB-856 WT Micron Technology Inc, MT45W1MW16BAFB-856 WT Datasheet - Page 16

• Manufacturer Part Number: MT45W1MW16BAFB-856 WT
• Description: IC PSRAM 16MBIT 85NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-856 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Low-Power Operation
Standby Mode Operation
Temperature Compensated Refresh
Partial Array Refresh
Deep Power-Down Operation
Configuration Registers
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
During standby, the device current consumption is reduced to the level necessary to per-
form the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE oper-
ation or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
Temperature compensated refresh (TCR) allows for adequate refresh at different tem-
peratures. This CellularRAM device includes an on-chip temperature sensor. When the
sensor is enabled, it continually adjusts the refresh rate according to the operating tem-
perature. The on-chip sensor is enabled by default.
Three fixed refresh rates are also available, corresponding to temperature thresholds of
+15°C, +45°C, and +85°C. The setting selected must be for a temperature higher than the
case temperature of the CellularRAM device. If the case temperature is +35°C, the system
can minimize self-refresh current consumption by selecting the +45°C setting. The
+15°C setting would result in inadequate refreshing and cause data corruption.
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map (see Table 6 on
page 26). READ and WRITE operations to address ranges receiving refresh will not be
affected. Data stored in addresses not receiving refresh will become corrupted. When re-
enabling additional portions of the array, the new portions are available immediately
upon writing to the RCR.
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled by rewriting the RCR, the CellularRAM device will require 150µs to perform
an initialization procedure before normal operations can resume. During this 150µs
period, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access
sequence; the RCR should be accessed using CRE instead.
Two user-accessible configuration registers define the device operation. The bus config-
uration register (BCR) defines how the CellularRAM interacts with the system memory bus
and is nearly identical to its counterpart on burst mode Flash devices. The refresh configu-
ration register (RCR) is used to control how refresh is performed on the DRAM array.
These registers are automatically loaded with default settings during power-up and can
be updated anytime the devices are operating in a standby state.
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2003 Micron Technology, Inc. All rights reserved.