MT45W1MW16BAFB-856 WT Micron Technology Inc, MT45W1MW16BAFB-856 WT Datasheet - Page 21

• Manufacturer Part Number: MT45W1MW16BAFB-856 WT
• Description: IC PSRAM 16MBIT 85NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-856 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bus Configuration Register
Figure 17:
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
on the 32Mb device only.
All must be set to "0"
Bus Configuration Register Definition
Reserved
BCR[19]
20
A[20]
0
1
Notes: 1. All burst WRITEs are continuous.
Register
BCR[15]
Select
0
1
Select RCR
Select BCR
19
A19
BCR[13]
Must be set to "0"
0
0
0
0
1
1
1
1
Reserved
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] HIGH, or through the configuration register
software sequence with DQ = 0001h on the third cycle.
A[18:16]
18–16
Synchronous burst access mode
Asynchronous access mode (default)
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
BCR[10]
BCR[12] BCR[11]
Register Select
0
1
0
0
1
1
0
0
1
1
Operating
BCR[8]
Mode
Operation Mode
0
1
15
A15
Active LOW
Active HIGH (default)
0
1
0
1
0
1
0
1
Must be set to "0"
Reserved
Asserted during delay
Asserted one data cycle before delay (default)
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
14
Latency Counter
A14
WAIT Polarity
A13
13 12 11
Latency
Counter
WAIT Configuration
A12A11 A10
Polarity
WAIT
10
Must be set to "0"
Reserved
9
A9
21
Configuration (WC)
WAIT
8
A8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BCR[6]
0
1
Must be set to "0"
Reserved
BCR[5]
Rising edge (default)
Not supported
7
A7
0
1
BCR[3]
Configuration (CC)
0
1
Full Drive (default)
1/4 Drive
Clock Configuration
Output Impedance
Clock
BCR[2]
6
0
0
0
1
A6
Burst no wrap (default)
Burst wraps within the burst length
Configuration Registers
BCR[1] BCR[0]
0
1
1
1
Impedance
Output
Burst Wrap (Note 1)
5
A5
©2003 Micron Technology, Inc. All rights reserved.
1
0
1
1
Must be set to "0"
Reserved
4 words
8 words
16 words
Continuous burst (default)
A4
4
Burst Length (Note 1)
Wrap (BW)*
Burst
A3
3
Length (BL)*
2
A2 A1 A0
Burst
1
0