MT45W1MW16BAFB-856 WT TR Micron Technology Inc, MT45W1MW16BAFB-856 WT TR Datasheet
MT45W1MW16BAFB-856 WT TR
Specifications of MT45W1MW16BAFB-856 WT TR
Related parts for MT45W1MW16BAFB-856 WT TR
MT45W1MW16BAFB-856 WT TR Summary of contents
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Async/Page/Burst CellularRAM MT45W2MW16BA MT45W1MW16BA* *Note: Please contact the factory for all new 16Mb designs. For the latest data sheet, refer to Micron’s Web site: Features • Single device supports asynchronous, page, and burst operations • ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Part-Numbering Information Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode Operation Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Low-Power Operation ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory List of Figures Figure 1: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2: Functional Block Diagram – 2 Meg x 16 and 1 Meg Figure 3: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4: Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 5: READ Operation (ADV = LOW .10 Figure 6: WRITE Operation (ADV = LOW .10 Figure 7: Page Mode READ Operation (ADV = LOW) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory List of Tables Table 1: VFBGA Ball Descriptions Table 2: Bus Operations – Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 3: Bus Operations – Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 4: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 5: Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 6: 32Mb Address Patterns for PAR (RCR[ .26 Table 7: 16Mb Address Patterns for PAR (RCR[ ...
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... To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a trans- parent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write per- formance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices ...
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... Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 2: Bus Operations – Asynchronous Mode Mode Power Active Read Write Active Standby Standby No Operation Idle Active Configuration Register Deep DPD Power-Down Table 3: Bus Operations – Burst Mode Mode Power Async Read Active ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM Memory Operating Core Voltage W = 1.70V–1.95V Address Locations M = Megabits Operating Voltage W = 1.70V– ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Functional Description In general, the MT45W2MW16BA and MT45W1MW16BA devices are high-density alter- natives to SRAM and Pseudo SRAM products popular in low-power, portable applications. The MT45W2MW16BA contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. The MT45W1MW16BA contains a 16,777,216-bit DRAM core orga- nized as 1,048,576 addresses by 16 bits ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 5: READ Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Note: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation ...
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... CellularRAM device. The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. Once the Cellular- RAM device has restored the previous row’ ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 8: Burst Mode READ (4-word Burst) CLK ADDRESS A[20:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# READ Burst Identified Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. ...
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... WRITE operation. CE# must return HIGH when transitioning between mixed- mode operations. Note that the time is required to ensure adequate refresh. Mixed-mode operation facilitates a seam- less interface to legacy burst mode Flash memory controllers. See Figure 43 on page 52 for the “Asynchronous WRITE Followed by Burst READ” timing diagram. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system- level WAIT signal (see Figure 10 below) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory tions, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 12: Refresh Collision During WRITE Operation V IH CLK VALID A[20:0] ADDRESS ADV LB#/UB WAIT High DQ[15: Additional WAIT states inserted to allow refresh completion. Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay ...
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... Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 6 on page 26) ...
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... WRITE operation when the configuration register enable (CRE) input is HIGH (see Fig- ure 13 on page 17 and Figure 14 on page 18). When CRE is LOW, a READ or WRITE oper- ation will access the memory array. The register values are placed on address pins A[20:0 asynchronous WRITE, the values are latched into the configuration regis- ter on the rising edge of ADV#, CE#, or WE#, whichever occurs first ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[20:0] OPCODE (except A19 A19 t SP CRE ADV CSP CE LB#/UB WAIT High-Z DQ[15:0] Notes: 1. Non-default BCR settings for CR WRITE in synchronous mode followed by READ ARRAY operation: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Software Access Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 15) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 16: Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Notes: 1. WRITE on third cycle must be CE# controlled. 2. CE# must be HIGH for 150ns before performing the cycle that reads a configuration regis- ter. PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2.fm - Rev. E 10/05 EN ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 4: Sequence and Burst Length 4-Word Burst Wrap Starting Burst Address Length BCR[3] Wrap (Decimal) Linear 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 Yes 6 7 ... 0-1-2-3 1 1-2-3-4 2 2-3-4-5 3 3-4-5 ... 14 15 Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during a burst READ oper- ation ...
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... The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfers during syn- chronous READ and WRITE operations. When BCR[ data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (Figures 18 and 20) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 20: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] Note: Non-default BCR setting for WAIT during burst operation: WAIT active LOW. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred ...
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... Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This fea- ture allows the device to reduce standby current by refreshing only that part of the mem- ory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 6: 32Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ Table 7: 16Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 8: Absolute Maximum Ratings Parameter Voltage to Any Ball Except Voltage on V Supply Relative Voltage Supply Relative Storage Temperature (plastic) Operating Temperature (case) Wireless (see Note 1) Industrial Soldering Temperature and Time 10 seconds (solder ball only) Stresses greater than those listed may cause permanent damage to the device ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 9: Electrical Characteristics and Operating Conditions Wireless Temperature Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Current ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Maximum and Typical Standby Currents The following tables and figures refer to the maximum and typical standby currents for the MT45W2MW16BA and MT45W1MW16BA devices. The typical values shown in Fig- ure 23 on page 30 and Figure 24 on page 31 are measured with the default on-chip tem- perature sensor control enabled ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 12: Maximum Standby Currents for Applying PAR and TCR Settings – 16Mb PAR Full Array 1/2 Array 1/4 Array 1/8 Array 0 Array Notes: 1. For RCR[6:5] = 00b (default) refer to Figure 24 on page 31 for typical values. ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 24: Typical Refresh Current vs. Temperature ( -30 -20 - Table 13: Deep Power-Down Specifications Description Deep Power-Down PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2.fm - Rev. E 10/05 EN Maximum and Typical Standby Currents ) – 16Mb TCR Temperature (°C) Conditions 0V; +25°C ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 14: Capacitance Description Input Capacitance Input/Output Capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100% tested. Figure 25: AC Input/Output Reference Waveform Input V SS Notes test inputs are driven at V times (10% to 90%) < 1.6ns. ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 16: Asynchronous READ Cycle Timing Requirements 1 Parameter Address Access Time ADV# Access Time Page Access Time Address Hold from ADV# HIGH Address Setup to ADV# HIGH LB#/UB# Access Time LB#/UB# Disable to DQ High-Z Output ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 17: Burst READ Cycle Timing Requirements 1 Parameter Burst to READ Access Time CLK to Output Delay Burst OE# LOW to Output Delay CE# HIGH between Subsequent Burst and Mixed-Mode Operations Maximum CE# Pulse Width CE# LOW to WAIT Valid CLK Period ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 18: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW Setup Time Address Hold from ADV# Going HIGH Address Setup to ADV# Going HIGH Address Valid to End of WRITE LB#/UB# Select to End of WRITE CE# LOW to WAIT Valid ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 19: Burst WRITE Cycle Timing Requirements Parameter CE# HIGH between Subsequent Burst and Mixed-Mode Operations Minimum CE# Pulse Width CE# LOW to WAIT Valid Clock Period CE# Setup to CLK Active Edge Hold Time from Active CLK Edge Chip Disable to WAIT High-Z Output ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 28: Asynchronous READ A[20:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 21: Asynchronous READ Timing Parameters -70x Symbol Min Max Min BHZ t 10 BLZ t CEW 1 7 PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2.fm - Rev. E 10/05 EN Maximum and Typical Standby Currents ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 29: Asynchronous READ Using ADV# A[20:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 22: Asynchronous READ Timing Parameters Using ADV# -70x Symbol Min Max Min AADV 70 t AVH AVS BHZ 8 t BLZ 7.5 CEW t CO ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 30: Page Mode READ A[20:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 23: Asynchronous READ Timing Parameters – Page Mode Operation -70x Symbol Min Max Min APA BHZ BLZ t CEM 8 t CEW 1 7 PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2 ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 31: Single-Access Burst READ Operation V IH CLK A[20:0] VALID ADDRESS ADV CSP LB#/UB CEW V OH WAIT High DQ[15:0] High READ Burst Identified (WE# = HIGH) Notes: 1. Non-default BCR settings for single-access burst READ operation: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 32: 4-Word Burst READ Operation V IH CLK A[20:0] VALID ADDRESS ADV CSP LB#/UB CEW V OH WAIT High DQ[15: READ Burst Identified (WE# = HIGH) Notes: 1. Non-default BCR settings for 4-word burst READ operation: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 33: 4-Word Burst READ Operation (with LB#/UB CLK VALID A[20:0] ADDRESS ADV CSP LB#/UB CEW V OH WAIT High DQ[15:0] High READ Burst Identified (WE# = HIGH) Notes: 1. Non-default BCR settings for 4-word burst READ operation with LB#/UB#: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 34: READ Burst Suspend V IH CLK VALID A[20:0] V ADDRESS ADV CSP LB#/UB OLZ High-Z WAIT DQ[15:0] High ACLK Notes: 1. Non-default BCR settings for READ burst suspend: Latency code two (three clocks); WAIT active LOW ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 35: Continuous Burst READ Showing an Output Delay with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[20: ADV LB#/ WAIT VALID DQ[15:0] OUTPUT V OL Notes: 1. Non-default BCR settings for continuous burst READ showing an output delay, BCR[ for end-of-row condition: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 36: CE#-Controlled Asynchronous WRITE A[20:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 29: Asynchronous WRITE Timing Parameters – CE#-Controlled -70x Symbol Min Max Min CEW 1 7 CPH PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2.fm - Rev. E 10/05 EN ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 37: LB#/UB#-Controlled Asynchronous WRITE A[20:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 30: Asynchronous WRITE Timing Parameters – LB#/UB#-Controlled -70x Symbol Min Max Min CEW 1 7 PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2.fm - Rev. E 10/05 EN ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 38: WE#-Controlled Asynchronous WRITE A[20:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 31: Asynchronous WRITE Timing Parameters – WE#-Controlled -70x Symbol Min Max Min 7.5 CEW PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2.fm - Rev. E 10/05 EN ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 39: Asynchronous WRITE Using ADV# A[20:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 32: Asynchronous WRITE Timing Parameters Using ADV# -70x Symbol Min Max Min AVH 5 t AVS CEW 1 7 PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46 Burst CellularRAM_32__2 ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 40: Burst WRITE Operation V IH CLK A[20:0] VALID ADDRESS ADV LB#/UB CSP CEW V OH WAIT High DQ[15: WRITE Burst Identified (WE# = LOW) Notes: 1. Non-default BCR settings for burst WRITE operation: Latency code two (three clocks); ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 41: Continuous Burst WRITE Showing an Output Delay with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[20: ADV LB#/ WAIT DQ[15:0] VALID INPUT V IL END OF ROW (A[6:0] = 7Fh) Notes: 1. Non-default BCR settings for continuous burst WRITE, BCR[ WAIT active LOW; WAIT asserted during delay ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 42: Burst WRITE Followed by Burst READ t CLK V IH CLK A[20:0] VALID V ADDRESS ADV LB#/UB CSP WAIT High DQ[15: High-Z IN/OUT V IL Notes: 1. Non-default BCR settings for burst WRITE followed by burst READ: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 43: Asynchronous WRITE Followed by Burst READ V IH CLK A[20:0] VALID ADDRESS VALID ADDRESS AVS t AVH VPH V IH ADV CVS t BW LB#/ WPH WE WAIT WHZ DQ[15: High-Z DATA DATA IN/OUT Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 44: Asynchronous WRITE Followed By Burst READ – ADV# LOW V IH A[20:0] VALID ADDRESS ADV LB#/ WPH WAIT WHZ V IH DQ[15:0] High-Z DATA IN/OUT Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code two (three clocks) ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 45: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[20:0] VALID ADDRESS ADV CSP LB#/UB CEW V OH WAIT DQ[15: READ Burst Identified (WE# = HIGH) Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: a) clocked CE# HIGH CE# HIGH for greater than 15ns ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 46: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[20:0] VALID ADDRESS ADV CSP LB#/UB CEW V OH WAIT DQ[15: READ Burst Identified (WE# = HIGH) Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: a) clocked CE# HIGH CE# HIGH for greater than 15ns ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 47: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW V IH A[20:0] VALID ADDRESS ADV LB#/ WPH WAIT WHZ V IH DQ[15:0] High-Z DATA IN/OUT Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITES ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 48: Asynchronous WRITE Followed by Asynchronous READ V IH A[20:0] VALID ADDRESS VPH V IH ADV LB#/ WAIT V OL DQ[15: High-Z IN/OUT V IL Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITES ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Figure 49: 54-Ball VFBGA SEATING PLANE C 0.10 C 54X Ø0.37 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø0.35. BALL A6 6.00 3.00 1.875 Notes: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Revision History Rev 10/05 • Added new 16Mb part-specific note. Rev 01/05 • Added 16Mb device. • Clarified data values in Figure 41 on page 50. • Corrected typographic error. • Removed 60ns and 104 MHz support. ...
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... Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory • Updated I • Corrected package diagram. • WE# LOW limited to • Last address changed by software access sequence. • Noted that the software access third cycle must be a CE#-controlled WRITE. • Separated I • Moved • CRE is “Don’t Care” during burst continue. ...