MT45W1MW16BAFB-856 WT TR Micron Technology Inc, MT45W1MW16BAFB-856 WT TR Datasheet - Page 26

• Manufacturer Part Number: MT45W1MW16BAFB-856 WT TR
• Description: IC PSRAM 16MBIT 85NS 54FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BAFB-856 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
Table 7:
Deep Power-Down (RCR[4]) Default = DPD Disabled
Temperature Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor
Page Mode Operation (RCR[7]) Default = Disabled
PDF: 09005aef80ec6f63/Source: 09005aef80ec6f46
Burst CellularRAM_32__2.fm - Rev. E 10/05 EN
RCR[2]
RCR[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RCR[1]
RCR[1]
32Mb Address Patterns for PAR (RCR[4] = 1)
16Mb Address Patterns for PAR (RCR[4] = 1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RCR[0]
RCR[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150µs to perform an initialization proce-
dure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to
“1.” DPD should not be enabled or disabled with the software access sequence; instead,
use CRE to access the RCR.
This CellularRAM device includes an on-chip temperature sensor that automatically
adjusts the refresh rate according to the operating temperature. The on-chip TCR is
enabled by clearing both of the TCR bits in the refresh configuration register (RCR[6:5] =
00b). Any other TCR setting enables a fixed refresh rate. When the on-chip temperature
sensor is enabled, the device continually adjusts the refresh rate according to the operat-
ing temperature.
The TCR bits also allow for adequate fixed-rate refresh at three different temperature
thresholds (+15°C, +45°C, and +85°C). The setting selected must be for a temperature
higher than the case temperature of the CellularRAM device. If the case temperature
is +35°C, the system can minimize self refresh current consumption by selecting the
+45°C setting. The +15°C setting would result in inadequate refreshing and cause
data corruption.
The page mode operation bit determines whether page mode is enabled for asynchro-
nous READ operations. In the power-up default state, page mode is disabled.
2 Meg x 16, 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
One-quarter of die
One-quarter of die
One-quarter of die
One-quarter of die
One-eighth of die
One-eighth of die
One-eighth of die
One-eighth of die
Active Section
Active Section
One-half of die
One-half of die
One-half of die
One-half of die
None of die
None of die
Full die
Full die
26
000000h–07FFFFh
000000h–03FFFFh
1C0000h–1FFFFFh
000000h–0FFFFFh
000000h–07FFFFh
000000h–03FFFFh
000000h–01FFFFh
000000h–1FFFFFh
000000h–0FFFFFh
100000h–1FFFFFh
180000h–1FFFFFh
000000h–0FFFFFh
C0000h–0FFFFFh
E0000h–0FFFFFh
Address Space
Address Space
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
0
Configuration Registers
2 Meg x 16
1 Meg x 16
0 Meg x 16
1 Meg x 16
1 Meg x 16
0 Meg x 16
512K x 16
256K x 16
512K x 16
256K x 16
512K x 16
256K x 16
128K x 16
512K x 16
256K x 16
128K x 16
Size
Size
©2003 Micron Technology, Inc. All rights reserved.
Density
Density
32Mb
16Mb
16Mb
16Mb
8Mb
4Mb
0Mb
8Mb
4Mb
8Mb
4Mb
2Mb
0Mb
8Mb
4Mb
2Mb