IC SDRAM 128MBIT 100MHZ 54VFBGA

 

MT48V8M16LFB4-10:G

Manufacturer Part NumberMT48V8M16LFB4-10:G
DescriptionIC SDRAM 128MBIT 100MHZ 54VFBGA
ManufacturerMicron Technology Inc
MT48V8M16LFB4-10:G datasheets

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Specifications of MT48V8M16LFB4-10:G

Format - MemoryRAMMemory TypeMobile SDRAM
Memory Size128M (8Mx16)Speed100MHz
InterfaceParallelVoltage - Supply2.3 V ~ 2.7 V
Operating Temperature0°C ~ 70°CPackage / Case54-VFBGA
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Functional Description
In general, the 128Mb SDRAMs (2 Meg x 16 x 4 banks and 1 Meg x 32 x 4 banks) are quad-
bank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s
33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the
x32’s 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (x16: A0–A8; x32: A0–A7) regis-
tered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER (LMR) command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to V
2. Assert and hold CKE at a LVTTL logic LOW.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, one or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
and V
Q (simultaneously) and the clock is stable (stable clock is
DD
DD
and V
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
15
128Mb: x16, x32 Mobile SDRAM
Functional Description
Q.
DD
©2001 Micron Technology, Inc. All rights reserved.

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