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MT48V8M16LFB4-10:G
MT48V8M16LFB4-10:G | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-10:G |
| Description | IC SDRAM 128MBIT 100MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-10:G datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
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- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of MT48V8M16LFB4-10:G | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 100MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less because both SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
Self refresh is not supported on automotive temperature (AT) devices.
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 10).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 11 on page 27, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Figure 10:
Activating a Specific Row in a Specific Bank
A0–A10, A11
BA0, BA1
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
t
RCD specification.
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
CK ≤ 3. (The same procedure is used to convert other
t
t
RCD (MIN)/
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
BANK
ADDRESS
DON’T CARE
26
128Mb: x16, x32 Mobile SDRAM
Register Definition
t
RCD (MIN) should be divided by
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
t
RC.
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