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MT48V8M16LFB4-10:G
MT48V8M16LFB4-10:G | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-10:G |
| Description | IC SDRAM 128MBIT 100MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-10:G datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MT48V8M16LFB4-10:G | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 100MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of 1), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
Figure 30:
Clock Suspend During READ Burst
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
Notes:
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CONCURRENT Auto Precharge
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 31 on page 42).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32 on page 42).
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
T0
T1
T2
T3
READ
NOP
NOP
BANK,
COL n
D
OUT
DQ
n
TRANSITIONING DATA
41
128Mb: x16, x32 Mobile SDRAM
T4
T5
T6
NOP
NOP
NOP
D
D
D
OUT
OUT
OUT
n + 1
n + 2
n + 3
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
READs
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