IC FLASH 8GBIT 48TSOP

 

MT29F8G08FACWP:C TR

Manufacturer Part NumberMT29F8G08FACWP:C TR
DescriptionIC FLASH 8GBIT 48TSOP
ManufacturerMicron Technology Inc
MT29F8G08FACWP:C TR datasheet
 

Specifications of MT29F8G08FACWP:C TR

Format - MemoryFLASHMemory TypeFLASH - Nand
Memory Size8G (1G x 8)InterfaceParallel
Voltage - Supply2.7 V ~ 3.6 VOperating Temperature0°C ~ 70°C
Package / Case48-TSOPLead Free Status / RoHS StatusLead free / RoHS Compliant
Speed-  
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NAND Flash Memory
MT29F2G08AACWP, MT29F4G08BACWP, MT29F8G08FACWP
For the latest data sheet, refer to the Micron Web site: www.micron.com/products/nand/
Features
• Organization
– Page size x8: 2,112 bytes (2,048 + 64 bytes)
– Page size x16: 1,056 words (1,024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks;
8Gb: 8,192 blocks
• READ performance
– Random READ: 25µs
– Sequential READ: 30ns (3V x8 only)
• WRITE performance
– PROGRAM PAGE: 300µs (TYP)
– BLOCK ERASE: 2ms (TYP)
• Endurance: 100,000 PROGRAM/ERASE cycles
• First block (block address 00h) guaranteed to be
valid without ECC (up to 1,000 PROGRAM/ERASE
cycles)
1
• V
: 1.70V–1.95V
or 2.7V–3.6V
CC
• Automated PROGRAM and ERASE
• Basic NAND Flash command set:
– PAGE READ, READ for INTERNAL DATA MOVE,
RANDOM DATA READ, READ ID, READ STATUS,
PROGRAM PAGE, RANDOM DATA INPUT, PRO-
GRAM PAGE CACHE MODE, PROGRAM for
INTERNAL DATA MOVE, BLOCK ERASE, RESET
• New commands:
– PAGE READ CACHE MODE
– One-time programmable (OTP), including:
OTP DATA PROGRAM, OTP DATA PROTECT,
OTP DATA READ
– READ UNIQUE ID (contact factory)
– READ ID2 (contact factory)
• Operation status byte provides a software method of
detecting:
– PROGRAM/ERASE operation completion
– PROGRAM/ERASE pass/fail condition
– Write-protect status
• READY/BUSY (R/B#) pin provides a hardware
method of detecting PROGRAM or ERASE cycle
completion
• WP# pin: hardware write protect
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__1.fm - Rev. D 12/06 EN
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory
Figure 1:
48-Pin TSOP Type 1
Options
• Density:
– 2Gb (single die)
– 4Gb (dual-die stack)
– 8Gb (quad-die stack)
• Device width:
– x8
1
– x16
• Configuration:
# of die # of CE# # of R/B#
1
1
2
1
4
2
• V
:
CC
– 2.7V–3.6V
1
– 1.70V–1.95V
• Third-generation die
• Package:
– 48-Pin TSOP type I (lead-free)
• Operating temperature:
– Commercial (0°C to 70°C)
– Extended (–40°C to +85°C)
Notes: 1. Packaged parts are only available for 3V x8
devices. For 1.8V or x16 devices, contact
factory.
2. For ET devices, contact factory.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
©2005 Micron Technology, Inc. All rights reserved.
Features
Marking
MT29F2G
MT29F4G
MT29F8G
MT29Fxx08x
MT29Fxx16x
1
A
1
B
2
F
A
B
C
WP
None
2
ET

MT29F8G08FACWP:C TR Summary of contents

  • Page 1

    ... WP# pin: hardware write protect PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__1.fm - Rev. D 12/06 EN Products and specifications discussed herein are subject to change by Micron without notice. 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Figure 1: 48-Pin TSOP Type 1 Options • Density: – 2Gb (single die) – ...

  • Page 2

    ... Micron Parametric Part Search at parametric. If the device required is not on this list, contact the factory. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__1.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory ® NAND Flash devices are available in several different configurations and A A ...

  • Page 3

    ... Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CC Timing Diagrams .44 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aTOC.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2005 Micron Technology, Inc. All rights reserved. Table of Contents ...

  • Page 4

    ... BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 54: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 55: TSOP Type PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aLOF.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2005 Micron Technology, Inc. All rights reserved. List of Figures ...

  • Page 5

    ... Table 21: AC Characteristics: Normal Operation Table 22: PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aLOT.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ©2005 Micron Technology, Inc. All rights reserved. List of Tables ...

  • Page 6

    ... NAND Flash technology provides a cost-effective solution for applications requiring high-density, solid-state storage. Micron MT29F2G08AxC and MT29F2G16AxC devices are 2Gb NAND Flash memory devices. The MT29F4G08BxC and MT29F4G16BxC are 4Gb devices. The MT29F8G08FAC is a four-die stack that operates as two independent 4Gb devices, providing a total storage capacity of 8Gb in a single, space-saving package. ...

  • Page 7

    ... WP# WP# DNU 20 DNU DNU DNU 21 22 DNU DNU Notes: 1. R/B2# and CE2# are available only on 8Gb devices. These pins are NC for other configurations. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Pin Assignments and Descriptions ...

  • Page 8

    ... For the 8Gb configuration, CE# controls the first 4Gb of memory; CE2# controls the second 4Gb. See “Bus Operation” on page 16 for additional operational details. In the 8Gb configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb of memory enabled by the CE2#. Command latch enable: When CLE is HIGH, information is transferred from I/O[7:0] to the on-chip command register on the rising edge of WE# ...

  • Page 9

    ... The internal memory array is accessed on a page basis. During reads, a page of data is copied from the memory array into the data register. Once copied to the data register, data is output sequentially, byte by byte on x8 devices, or word by word on x16 devices ...

  • Page 10

    ... Bytes 2,112 through 4,095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 2 • • • • • • • • • • • • • ...

  • Page 11

    ... Words 1,056 through 2,048 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 2 • • • • • • • • • • • • • ...

  • Page 12

    ... Notes CA11 = “1” then CA[10:6] must be “0.” 2. Block address concatenated with page address = actual page address; CAx = column address; PAx = page address; BAx = block address. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 2,112 bytes 2,048 64 2,048 ...

  • Page 13

    ... Block address concatenated with page address = actual page address. CAx = column address; PAx = page address, BAx = block address. 3. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 1,056 words 1,024 32 1,024 ...

  • Page 14

    ... Die address boundary: “0” = 0Gb–2Gb devices; “1” = 2Gb–4Gb devices. 3. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 2,112 bytes 2,048 64 2,048 ...

  • Page 15

    ... Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 4. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 1,056 words 1,024 32 1,024 ...

  • Page 16

    ... Care” operations. The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn- chronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus ...

  • Page 17

    ... Data is input on I/O[7:0] for x8 devices, and on I/O[15:0] for x16 devices. See Figure 36 on page 45 for additional data input details. READs After a READ command is issued, data is transferred from the memory array to the data register on the rising edge of WE#. R/B# goes LOW for transfer is complete. When R/B# goes HIGH, data is available in the data register clocked out of the part by toggling RE# ...

  • Page 18

    ... Notes: 1. Fall and t 2. Rise is primarily dependent on external pull-up resistor and external capacitive loading. t Fall ≈ 10ns at 3.3V; 3. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Rp R/B# Open drain output I OL Device t t Fall Rise ...

  • Page 19

    ... Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby Logic level HIGH Logic level LOW PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 Rp (Ω) ...

  • Page 20

    ... INTERNAL DATA MOVE. 3. RANDOM DATA READ command is limited to use within a single page. 4. RANDOM DATA INPUT command is limited to use within a single page. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Number of Data Command Address Cycles ...

  • Page 21

    ... WE# ALE RE# Col 00h I/Ox add 1 add 2 R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t R), monitor the R/B# signal, or, alternatively, issue a READ STATUS (70h) com- Col Row Row Row add 1 add 2 add 3 21 Command Definitions ...

  • Page 22

    ... First, a normal PAGE READ (00h-30h) command sequence is issued. See Figure 16 on page 23 for operation details. The R/B# signal goes LOW for transfer the first page of data from the memory to the data register. After R/B# returns to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the com- mand register ...

  • Page 23

    Figure 16: PAGE READ CACHE MODE CLE CE# WE# ALE t R R/B# RE# I/Ox 00h Address (5 cycles) 30h t DCBSYR1 t DCBSYR2 31h Data output 31h (Serial access) (Serial access) t DCBSYR2 Data output 3Fh Data output (Serial ...

  • Page 24

    ... CLE CE# WE# ALE RE# 90h I/Ox Address, 1 Ccycle Notes: 1. See Table 10 on page 25 for byte definitions. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory WHR t REA 00h Byte 0 Byte 1 24 Command Definitions Byte 2 Byte 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 25

    ... Notes binary hex. 2. Device IDs for these configurations are provided for reference only. 3. The MT29F8G08FAC device ID code reflects the configuration of each 4Gb section. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory I/O7 I/O6 I/O5 I/O4 ...

  • Page 26

    ... See Figure 16 on page 23 and Figure 21 on page 28. Figure 18: Status Register Operation CE# CLE WE# RE# I/Ox PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Page Read Page Read Cache Mode – – – – – – ...

  • Page 27

    ... PROGRAM and READ STATUS Operation R/B# 80h Address (5 cycles) I/Ox Figure 20: RANDOM DATA INPUT R/B# I/Ox 80h Address (5 cycles) D PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t PROG D 10h IN 85h Address (2 cycles Command Definitions t PROG. The READ STATUS ...

  • Page 28

    ... Notes: 1. See Note 3, Table 22 on page 43. 2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass fail. RE# can stay LOW or pulse multiple times after a 70h command. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t CBSY Address/ Address/ 80h ...

  • Page 29

    ... The written column addresses are ignored even though all 5 ADDRESS cycles are required. The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE command. Refer to the command description in the following section for details. PROGRAM for INTERNAL DATA MOVE 85h-10h ...

  • Page 30

    ... Figure 23: INTERNAL DATA MOVE with RANDOM DATA INPUT R/B# Address I/Ox 00h 35h (5 cycles) PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t R Address 85h (5 cycles Address 85h Data 85h (5 cycles) Unlimited number ...

  • Page 31

    ... CE# WE# ALE R/B# RE# 60h I/Ox Address input (3 cycles) PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t BERS D0h Micron Technology, Inc., reserves the right to change products or specifications without notice. 31 Command Definitions t BERS 70h Status I ERASE successful I ERASE error Don’ ...

  • Page 32

    ... One-Time Programmable (OTP) Area This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Ten full pages (2,112 bytes or 1,056 words per page) of OTP data is available on the device, and the entire range is guaranteed to be good from the factory. ...

  • Page 33

    ... Col Col I/Ox A0h add 1 add 2 OTP DATA INPUT command R/B# Notes: 1. The OTP page must be within the 02h–0Bh range. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory OTP page 00h bytes serial input ...

  • Page 34

    ... Col I/Ox A5h 00h OTP DATA PROTECT command R/B# Notes: 1. OTP data is protected following “good” status confirmation. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Col 01h 00h 00h 10h 00h PROGRAM command 34 Command Definitions t PROG ...

  • Page 35

    ... R/B# Notes: 1. The OTP page must be within the 02h–0Bh range. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t R) while the data is moved from the OTP page to the data register. The Col OTP ...

  • Page 36

    ... RESET Operation RESET FFh The RESET command is used to put the memory device into a known condition and to abort a command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid ...

  • Page 37

    ... I/Ox WP# R/B# Figure 31: PROGRAM Enable WE# I/Ox WP# R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t WW 60h D0h t WW 60h D0h t WW 80h 10h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 38

    ... Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, certain pre- cautions must be taken: • ...

  • Page 39

    ... NAND Flash to initialize before any commands are executed (see Figure 33). Figure 33: AC Waveforms During Power Transitions Vcc WP# WE# R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory SS MT29FxGxxxAC MT29FxGxxxBC MT29FxGxxxAC MT29FxGxxxBC Symbol Commercial T A ...

  • Page 40

    ... Input high voltage CE#, CLE, ALE, WE#, RE#, WP#, R/B# Input low voltage (all inputs) Output high voltage Output low voltage Output low current (R/B#) PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Conditions Symbol ; I = 0mA I IL OUT CC – ...

  • Page 41

    ... Block 00h (the first block) is guaranteed to be valid and does not require error correction up to 1,000 PROGRAM/ERASE cycles. 3. The number of invalid blocks in each 4Gb section will not exceed 80. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Conditions ; I = 0mA IL OUT – ...

  • Page 42

    ... For PAGE READ CACHE MODE and PROGRAM PAGE CACHE MODE operations, the 3V x16 AC characteristics apply for 3V x8 devices. 3. For 1.8V devices: During PROGRAM PAGE CACHE MODE and PAGE READ CACHE MODE operations, when V PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Symbol Device C MT29F2GxxAxC IN ...

  • Page 43

    ... CBSY MAX time depends on timing between internal program completion and data in LPROG = address load time (last page) – data load time (last page). PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 3V x16 and 1.8V Symbol Min Max t 10 ...

  • Page 44

    ... I/O[15:8] must be set to “0.” Figure 35: ADDRESS LATCH Cycle CLE CE# WE# ALE I/Ox Note: x16: I/O [15:8] must be set to “0.” PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t CLS t CLH ALH t ALS Command t CLS ...

  • Page 45

    ... INPUT DATA LATCH Cycle CLE CE# ALE WE# I/Ox Notes Figure 37: SERIAL ACCESS Cycle After READ t CEA CE# t REA t RP RE# I/ R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t ALS Final = 2,111 (x8) or 1,055 (x16). t REA t REH t RHZ ...

  • Page 46

    ... RE# I/Ox Figure 39: PAGE READ Operation CLE CE WE# ALE RE# Col 00h I/Ox add 1 add 2 R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t CLR t CLS t CLH WHR 70h Col Row Row Row add 1 add 2 add 3 46 ...

  • Page 47

    ... RANDOM DATA READ Operation CLE CE# WE# ALE RE# Col Col Row I/Ox 00h add 1 add 2 add1 Column address N R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t R 30h t CEA CE# t REA RE# Out I/ Row Row OUT ...

  • Page 48

    Figure 42: PAGE READ CACHE MODE Operation, Part CLE t CLH t CLS CE WE# ALE RE Col Col Row Row I/Ox 00h add 1 add 2 ...

  • Page 49

    Figure 43: PAGE READ CACHE MODE Operation, Part CLE t CLS t CLH CE# WE# t CEA ALE REA D OUT ...

  • Page 50

    Figure 44: PAGE READ CACHE MODE Operation without R/B#, Part CLE t CLS t CLH CE WE# ALE RE Col Col Row Row Row I/Ox 00h add ...

  • Page 51

    Figure 45: PAGE READ CACHE MODE Operation without R/B#, Part CLE t CLS t CLH CE# WE# t CEA ALE REA D D I/Ox OUT ...

  • Page 52

    ... WC WE# ALE RE# Col Col I/Ox 80h add 1 add 2 SERIAL DATA INPUT command R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory WHR t REA 00h Byte 0 Byte 1 t ADL Row Row Row D IN add 1 add 2 add 3 ...

  • Page 53

    ... WE# ALE RE# Col Col Row Row I/Ox 80h add 1 add 2 add 1 add 2 SERIAL DATA INPUT command R/B# PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Data input CE WE# t ADL Row D D Col IN IN 85h add 3 N N+1 ...

  • Page 54

    ... Row Row I/Ox 80h add 1 add 2 add 1 add 2 add 3 SERIAL DATA INPUT R/B# Last Page - 1 PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory Row Col Col Row 35h 85h add 1 add 2 add 1 add 3 Busy INTERNAL ...

  • Page 55

    Figure 52: PROGRAM PAGE CACHE MODE Operation Ending on 15h CLE CE ADL WE# ALE RE# Col Col Row Row Row I/Ox 80h N M add 1 add 2 add 1 add 2 add ...

  • Page 56

    ... Notes: 1. See Table 10 on page 25 for actual values. Figure 54: RESET Operation CLE CE# WE# R/B# I/Ox FFh RESET command PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory BERS Row D0h add 3 ERASE command Busy RST 56 Timing Diagrams ...

  • Page 57

    ... Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory 20.00 ±0.25 18.40 ±0.08 See detail A 1.20 MAX ® ...

  • Page 58

    ... Rev 4/06 • Table 21 on page 43: Updated the and 1.8V devices. Rev 3/06 • Initial release. PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN 2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory t CHZ MAX value to 45ns (MAX) from 100ns to 150ns timings with R/B# unde- ...