MT29F8G08FACWP:C TR Micron Technology Inc, MT29F8G08FACWP:C TR Datasheet - Page 16

IC FLASH 8GBIT 48TSOP

MT29F8G08FACWP:C TR

Manufacturer Part Number
MT29F8G08FACWP:C TR
Description
IC FLASH 8GBIT 48TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08FACWP:C TR

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Bus Operation
Control Signals
Commands
Address Input
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins. I/O pins I/O[15:8] are used only for data in the x16 configura-
tion. Addresses and commands are always supplied on I/O[7:0].
The command sequence normally consists of a command latch cycle, an ADDRESS
LATCH cycle, and a DATA cycle—either READ or WRITE.
CE#, WE#, RE#, CLE, ALE and WP# control NAND Flash device READ and WRITE opera-
tions. On the 8Gb MT29F8G08FAC, CE# and CE2# each control independent 4Gb arrays.
CE2# functions the same as CE# for its own array; all operations described for CE# also
apply to CE2#.
CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the NAND Flash memory will accept command, data, and address information.
When the device is not performing an operation, CE# is typically driven HIGH and the
device enters standby mode. The memory will enter standby if CE# goes HIGH while
data is being transferred and the device is not busy. This helps reduce power consump-
tion. See Figure 40 on page 47 and Figure 48 on page 53 for examples of CE# “Don’t
Care” operations.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus. One device can be programmed while another is being read.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an address input cycle is occurring.
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are LOW, and
• CLE is HIGH, and
• the device is not busy.
The exceptions to this are the READ STATUS and RESET commands when busy. See
Figure 34 on page 44 for detailed timing requirements.
Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must
be written with zeros when a command is issued.
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are LOW, and
• ALE is HIGH, and
• the device is not busy.
Addresses are input on I/O[7:0] only; bits not part of the address space must be LOW.
For devices with a x16 interface, I/O[15:8] must be written with zeros when an address is
issued.
The number of ADDRESS cycles required for each command varies. Refer to the com-
mand descriptions to determine addressing requirements (see Table 9 on page 20).
16
2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Bus Operation

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