MT29F8G08FACWP:C TR Micron Technology Inc, MT29F8G08FACWP:C TR Datasheet - Page 27

IC FLASH 8GBIT 48TSOP

MT29F8G08FACWP:C TR

Manufacturer Part Number
MT29F8G08FACWP:C TR
Description
IC FLASH 8GBIT 48TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08FACWP:C TR

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
PROGRAM Operations
PROGRAM PAGE 80h-10h
SERIAL DATA INPUT 80h
RANDOM DATA INPUT 85h
Figure 19:
Figure 20:
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN
R/B#
I/Ox
R/B#
I/Ox
80h
80h
PROGRAM and READ STATUS Operation
RANDOM DATA INPUT
Address (5 cycles)
Address (5 cycles)
Micron NAND Flash devices are inherently page-programmed devices. Pages must be
programmed consecutively within a block, from the least significant page address to the
most significant page address (i.e., 0, 1, 2, …, 63). Random page address programming is
prohibited.
Micron NAND Flash devices also support partial-page programming operations. This
means that any single bit can only be programmed one time before an erase is required;
however, the page can be partitioned such that a maximum of eight programming oper-
ations are allowed before an erase is required.
PROGRAM PAGE operations require loading of the SERIAL DATA INPUT (80h) com-
mand into the command register, followed by five ADDRESS cycles, then the data. Serial
data is loaded on consecutive WE# cycles, starting at the given address. The PROGRAM
(10h) command is written after the data input is complete. The control logic automati-
cally executes the proper algorithm and controls all the necessary timing to program
and verify the operation. Write verification only detects “1s” that are not successfully
written to “0s.”
R/B# goes LOW for the duration of array programming time,
(70h) command and the RESET (FFh) command are the only commands valid during the
programming operation. Bit 6 of the status register will reflect the state of R/B#. When
the device reaches ready, read bit 0 of the status register to determine if the program
operation passed or failed (see Figure 19). The command register stays in read status
register mode until another valid command is written to it.
After the initial data set is input, additional data can be written to a new column address
with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-
mand can be used any number of times in the same page before the PAGE WRITE (10h)
command is issued. See Figure 20 for the proper command sequence.
D
IN
D
85h
IN
Address (2 cycles)
10h
t PROG
27
2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory
D
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10h
70h
t PROG
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
Command Definitions
t
Status
PROG. The READ STATUS
70h
©2005 Micron Technology, Inc. All rights reserved.
Status

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