MT29F8G08FACWP:C TR Micron Technology Inc, MT29F8G08FACWP:C TR Datasheet - Page 28

• Manufacturer Part Number: MT29F8G08FACWP:C TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08FACWP:C TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

PROGRAM PAGE CACHE MODE 80h-15h
Figure 21:
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN
R/B#
I/Ox
R/B#
I/Ox
80h
80h
data input
data input
PROGRAM PAGE CACHE MODE Example
Address/
Address/
Notes: 1. See Note 3, Table 22 on page 43.
15h
15h
Cache programming is actually a buffered programming mode of the standard PRO-
GRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by five address cycles and a full or
partial page of data. The data is initially copied into the cache register, and the CACHE
WRITE (15h) command is then latched to the command register. Data is transferred
from the cache register to the data register on the rising edge of WE#. R/B# goes LOW
during this transfer time. After the data has been copied into the data register and R/B#
returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and sub-
sequent programming passes, transfer from the cache register to the data register is held
off until current data register content has been programmed into the array.
Bit 6 (cache R/B#) of the status register can be read by issuing the READ STATUS (70h)
command to determine when the cache register is ready to accept new data. The R/B#
pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the
CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used
every time, including the last page of the programming sequence, status register bit 5
must be used to determine when programming is complete (see Figure 21).
Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-
tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”
(ready state) (see Figure 21).
t CBSY
2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass fail. RE# can stay LOW or
t CBSY
pulse multiple times after a 70h command.
70h
80h
output
Status
data input
Address/
2
A: Without status reads
80h
B: With status reads
15h
data input
Address/
t CBSY
28
2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory
80h
10h
data input
Address/
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t LPROG
70h
1
15h
output
Status
t CBSY
2
80h
Command Definitions
data input
©2005 Micron Technology, Inc. All rights reserved.
Address/
10h
t LPROG
1