MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 10

IC FLASH 8GBIT 48TSOP

MT29F8G08BAAWP:A TR

Manufacturer Part Number
MT29F8G08BAAWP:A TR
Description
IC FLASH 8GBIT 48TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08BAAWP:A TR

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Table 1:
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
R/B#, R/B2#
CE#, CE2#
Symbol
I/O[7:0]
DNU
WE#
WP#
ALE
CLE
RE#
(x8)
V
V
NC
CC
SS
Signal Descriptions
Output
Supply
Supply
Input
Input
Input
Input
Input
Input
Type
I/O
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register on the rising edge of
WE#
Chip enable: Gates transfers between the host system and the NAND Flash device.
After the device starts a PROGRAM or ERASE operation, CE# can be de-asserted.
For the 8Gb configuration, CE# controls the first 4Gb of memory; CE2# controls
the second 4Gb of memory. For the 16Gb configuration, CE# controls the first 8Gb
of memory; CE2# controls the second 8Gb. See “Bus Operation” on page 15 for
additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, CLE should be driven LOW.
Read enable: Gates transfers from the NAND Flash device to the host system.
Write enable: Gates transfers from the host system to the NAND Flash device.
Write protect: Protects against inadvertent PROGRAM and ERASE operations. All
PROGRAM and ERASE operations are disabled when WP# is LOW.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction
information. Data is output only during READ operations; at other times the I/Os
are inputs.
Ready/busy: An open-drain, active-LOW output, that uses an external pull-up
resistor. R/B# is used to indicate when the chip is processing a PROGRAM or ERASE
operation. It is also used during READ operations to indicate when data is being
transferred from the array into the serial data register. When these operations
have completed, R/B# returns to the High-Z state. In the 8Gb configuration, R/B# is
for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb of memory enabled
by CE2#. In the 16Gb configuration, R/B# is for the 8Gb of memory enabled by
CE#; R/B2# is for the 8Gb of memory enabled by CE2#.
V
V
No connect: NCs are not internally connected. They can be driven or left
unconnected.
Do not use: DNUs must be left unconnected.
CC
SS
: Ground connection.
: Power supply.
.
When address information is not being loaded, ALE should be driven LOW.
10
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
General Description
©2006 Micron Technology, Inc. All rights reserved.

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