MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 28

• Manufacturer Part Number: MT29F8G08BAAWP:A TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08BAAWP:A TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Figure 17:
Figure 18:
PROGRAM PAGE CACHE MODE 80h-15h
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
PROGRAM and READ STATUS Operation
RANDOM DATA INPUT Operation
R/B#
R/B#
Cache programming is actually a buffered programming mode of the standard
PROGRAM PAGE command. Programming is started by loading the SERIAL DATA
INPUT (80h) command to the command register, followed by 5 cycles of address and a
full or partial page of data. The data is initially copied into the cache register, and the
CACHE PROGRAM (15h) command is then latched to the command register. Data is
transferred from the cache register to the data register on the rising edge of WE#. R/B#
goes LOW during this transfer time. After the data has been copied into the data register
and R/B# returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and
subsequent programming passes, transfer from the cache register to the data register is
held off until current data register content has been programmed into the array.
The PROGRAM PAGE CACHE MODE command can cross block address boundaries; it
must not cross die address boundaries. RANDOM DATA INPUT (85h) commands are
permitted with PROGRAM PAGE CACHE MODE operations.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h)
command to determine when the cache register is ready to accept new data. The R/B#
pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the
CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used
every time, including the last page of the programming sequence, status register bit 5
must be used to determine when programming is complete (see Figure 19 on page 29).
I/Ox
I/Ox
80h
80h
Address (5 cycles)
Address (5 cycles)
D
IN
D
85h
IN
28
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
10h
Address (2 cycles)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t PROG
D
IN
10h
70h
t PROG
Command Definitions
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
©2006 Micron Technology, Inc. All rights reserved.
Status
70h
Status