MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 29

• Manufacturer Part Number: MT29F8G08BAAWP:A TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08BAAWP:A TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Figure 19:
Internal Data Move
READ FOR INTERNAL DATA MOVE 00h-35h
PROGRAM for INTERNAL DATA MOVE 85h-10h
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
PROGRAM PAGE CACHE MODE Operation Example
Notes:
Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-
tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”
(ready state) as shown in Figure 19.
R/B#
R/B#
1. See Note 3, Table 19 on page 64.
2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass/fail status. RE# can stay LOW
An internal data move requires two command sequences. Issue a READ for INTERNAL
DATA MOVE (00h-35h) command first, then the PROGRAM for INTERNAL DATA MOVE
(85h-10h) command. Data moves are only supported within the plane from which data is
read. Moving data from odd to even blocks, from even to odd blocks, and across die
boundaries is prohibited.
The READ for INTERNAL DATA MOVE (00h-35h) command is used in conjunction with
the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. First, 00h is written to
the command register, then the internal source address is written (5 cycles). After the
address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the
command register. This transfers a page from memory into the cache register.
The written column addresses are ignored even though all 5 ADDRESS cycles are
required.
The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE
command. Please refer to the description of this command in the following section.
After the READ for INTERNAL DATA MOVE (00h-35h) command has been issued and
R/B# goes HIGH, the PROGRAM for INTERNAL DATA MOVE (85h-10h) command can
be written to the command register. This command transfers the data from the cache register
to the data register and programming of the new destination page begins. The sequence:
85h, destination address (5 cycles), then 10h, is written to the device. After 10h is written,
R/B# goes LOW while the control logic automatically programs the new page. The READ
I/Ox
I/Ox
or pulse multiple times after a 70h command.
80h
80h
data input
data input
Address &
Address &
15h
15h
t CBSY
t CBSY
70h
80h
output
Status
data input
Address &
29
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
2
A: Without status reads
80h
B: With status reads
15h
data input
Address &
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CBSY
80h
10h
Address &
data input
t
LPROG
70h
1
15h
output
Status
Command Definitions
t CBSY
2
©2006 Micron Technology, Inc. All rights reserved.
80h
data input
Address &
10h
t
LPROG
1