MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 43

• Manufacturer Part Number: MT29F8G08BAAWP:A TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08BAAWP:A TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-80h-10h
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
The memory device is now ready to accept the TWO-PLANE PROGRAM for INTERNAL
DATA MOVE (85h-11h-80h-10h) command.
After the TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command has
been issued and R/B# goes HIGH (or the status register bit 6 is “1”), the TWO-PLANE
PROGRAM for INTERNAL DATA MOVE (85h-11h-80h-10h) command is used. Pages
must be read from and programmed to the same plane.
First, write 85h to the command register, then write the first-plane destination address
(5 cycles), then write 11h to the command register. The 11h command is a “dummy”
command that informs the control logic that the first set of data for the first plane is
complete. No programming of the NAND Flash array occurs. R/B# goes LOW for
then returns HIGH. The READ STATUS (70h) command also indicates that the device is
ready when status register bit 6 is set to “1.” The only valid commands during
READ STATUS (70h) and RESET (FFh).
After
second-plane destination address (5 cycles), then write 10h to the command register.
Data is transferred from the cache registers to the data registers on the rising edge of
WE#, and programming begins on both planes.
R/B# goes LOW for the duration of array programming time,
ming and verification are complete, R/B# returns HIGH. The READ STATUS (70h)
command also indicates that the device is ready when status register bit 6 is set to “1.”
The only valid commands during
PLANE/MULTIPLE-DIE READ STATUS (78h), and RESET (FFh).
If the READ STATUS (70h) command indicates an error in the operation (status register
bit 0 = 1), use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twice—
once for each plane—to determine which plane operation failed.
During the serial data input for either plane, the RANDOM DATA INPUT (85h)
command can be used any number of times to change the column address within that
plane. For details on this command, see “RANDOM DATA INPUT 85h” on page 27. See
Figure 32 on page 44 for an example.
t
DBSY, write the 80h (or 81h) command to the command register, then write the
43
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
t
PROG are READ STATUS (70h), TWO-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command Definitions
t
PROG. When program-
©2006 Micron Technology, Inc. All rights reserved.
t
DBSY are
t
DBSY,