MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 46

• Manufacturer Part Number: MT29F8G08BAAWP:A TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08BAAWP:A TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

TWO-PLANE/MULTIPLE-DIE READ STATUS 78h
Figure 34:
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle
In Micron NAND Flash devices that have two planes, and possibly more than one die in
a package that share the same CE# pin, it is possible to independently poll the status
register of a particular plane and die using the TWO-PLANE/MULTIPLE-DIE READ
STATUS (78h) command. This command can be used to check the status register during
and after two-plane operations (with the exception of TWO-PLANE PAGE READ), and to
check the status of interleaved die operations.
After the 78h command is issued, the device requires 3 ADDRESS cycles containing the
block and page addresses, BA[18:6] and PA[5:0]. The most significant block address bit
in the third ADDRESS cycle, BA18, selects the proper die, and the least significant block
address bit in the first ADDRESS cycle, BA6, selects the proper plane within that die.
After the 78h command and the 3 ADDRESS cycles, the status register is output on
I/O[7:0] when RE# is LOW. Changes in the status register will be seen on I/O[7:0] as long
as CE# and RE# are LOW; it is not necessary to issue a new TWO-PLANE/MULTIPLE-DIE
READ STATUS command to see these changes. The status register bit definitions are
identical to those reported by the READ STATUS (70h) command (see Table 9 on
page 26).
In devices that have more than one die sharing a common CE# pin, when one die is not
busy (status register bit 5 is “1”), it is possible to initiate a new operation to that die even
if the other die is busy (see “Interleaved Die Operations” on page 47).
If both die are busy during or following an interleaved die operation, the READ STATUS
(70h) command must not be used to check status, as both die will respond, causing bus
contention on I/O[7:0]. The TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command is required to check status during and after interleaved die operations.
Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited
during and following power-on RESET and OTP commands.
WE#
I/Ox
CE#
CLE
ALE
RE#
78h
46
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Address (3 cycles)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WHR
Command Definitions
t AR
©2006 Micron Technology, Inc. All rights reserved.
t REA
Status output