MT29F8G08BAAWP:A TR Micron Technology Inc, MT29F8G08BAAWP:A TR Datasheet - Page 47

• Manufacturer Part Number: MT29F8G08BAAWP:A TR
• Description: IC FLASH 8GBIT 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08BAAWP:A TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Interleaved Die Operations
Interleaved PROGRAM PAGE Operations
Figure 35:
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
I/Ox
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
80h
Address
Interleaved PROGRAM PAGE Operation with R/B# Monitoring
Die 1
Data
10h
In devices that have more than one die sharing a common CE# pin, it is possible to
significantly improve performance by interleaving operations between the die. When
both die are idle (R/B# is HIGH or status register bit 5 is “1”), issue a command to the
first die (BA18 = 0). Then, while the first die is busy (R/B# is LOW), issue a command to
the other die (BA18 = 1).
There are two ways to verify operation completion in each die: using the R/B# signal, or
monitoring the status register. R/B# remains LOW while either die is busy. When R/B#
goes HIGH, then both die are idle and the operations are complete. Alternatively, the
TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command can report the status of
each die individually. If a die is performing a cache operation, like PROGRAM PAGE
CACHE MODE (80h-15h) or TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-
80h-15h), then the die is able to accept the data for another cache operation when status
register bit 6 is “1.” All operations, including cache operations, are complete on a die
when status register bit 5 is “1.”
During and following interleaved die operations, the READ STATUS (70h) command is
prohibited. Instead, use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command. This command selects which die will report status. Interleaved two-plane
commands must also meet the requirements in “Two-Plane Addressing” on page 35.
PROGRAM PAGE, PROGRAM PAGE CACHE MODE, TWO-PLANE PROGRAM PAGE,
TWO-PLANE PROGRAM PAGE CACHE MODE, BLOCK ERASE, and TWO-PLANE BLOCK
ERASE can be used as interleaved operations on separate die that share a common CE#.
Figures 35 and 36 show how to perform two types of interleaved PROGRAM PAGE oper-
ations. In Figure 35, the R/B# signal is monitored for operation completion. In Figure 36
on page 48, the status register is monitored for operation completion with the TWO-
PLANE/MULTIPLE-DIE READ STATUS (78h) command.
RANDOM DATA INPUT (85h) is permitted during interleaved PROGRAM PAGE
operations.
80h
Address
Die 2
Data
10h
47
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
80h
Address
Die 1
Data
10h
Command Definitions
©2006 Micron Technology, Inc. All rights reserved.
80h
Address
Die 2
Data
10h