MT48H32M16LFCJ-75 L IT:A TR Micron Technology Inc, MT48H32M16LFCJ-75 L IT:A TR Datasheet
MT48H32M16LFCJ-75 L IT:A TR
Specifications of MT48H32M16LFCJ-75 L IT:A TR
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MT48H32M16LFCJ-75 L IT:A TR Summary of contents
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Mobile SDRAM MT48H32M16LF – 8 Meg banks MT48H16M32LF/LG – 4 Meg banks Features • Fully synchronous; all signals registered on positive edge of system clock • 1.7–1.95V ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 512Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Meg x 32 General Description The Micron memory containing 536,870,912-bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1K columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by 512 columns by 32 bits reduced page-size option, each of the x32’ ...
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... The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address ...
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... PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM BANK1 13 BANK0 ROW- 13 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 8,192 LATCH ARRAY AND (8,192 x 512 x 32) DECODER SENSE AMPLIFIERS 16,384 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH ...
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Ball Assignments Figure 4: 54-Ball FBGA (Top View) – 10mm x 11.5mm Notes: 1. The E2 pin is a test pin and must be tied to V PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm ...
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Figure 5: 90-Ball VFBGA (Top View) – 10mm x 13mm Notes: 1. The K2 “DNU” ball should not be used in the application. However, it ...
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... A0–A12) and READ/WRITE command [column-address A0–A8 (x32); column-address A0–A9 (x16); with A10 defining auto precharge] to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command ...
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Table 3: VFBGA Ball Descriptions (Continued) 54-Ball VFBGA 90-Ball VFBGA A8, B9, B8, C9, R8, N7, R9, N8, C8, D9, D8, E9, P9, M8, M7, L8, E1, D2, D1, C2, L2, M3, M2, P1, C1, B2, B1, A2 N2, R1, ...
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Functional Description In general, the 512Mb SDRAMs (4 Meg banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read ...
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The mode registers must be loaded when all banks are idle, and the controller must wait t MRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses ...
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Figure 6: Mode Register Definition A12 BA1 BA0 M14 M13 M12 M14 M13 Mode Register Definition 0 0 Base mode register 1 0 Reserved 0 1 Extended mode register 1 1 Reserved M9 Write Burst ...
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Table 4: Burst Definition Table Burst Length CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency ...
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Extended Mode Register (EMR) The EMR controls the functions beyond those controlled by the mode register. These additional functions are special features of the mobile device that helps reduce overall system power consumption. They include temperature-compensated self refresh (TCSR) control, ...
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... Partial-Array Self Refresh (PASR) For further power savings during self refresh, the partial-array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during self refresh. The following refresh options are available. 1. All banks (banks and 3). ...
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WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks or segments of a bank in PASR will be refreshed during self refresh important to note that data in unused banks ...
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Commands Table 5 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear on pages 41–44; these tables provide current state/next state information. Table 5: Truth Table – ...
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... Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location ...
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Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge func- tion described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE ...
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... Deep Power-Down Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Array data will not be retained once the device enters deep power-down mode. This mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# held HIGH at the rising edge of the clock, while CKE is LOW ...
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Figure 9: Activating a Specific Row in a Specific Bank CLK CKE CS# RAS# CAS# WE# A0–A12 BA0, BA1 Figure 10: Example: Meeting CLK COMMAND READs READ bursts are initiated with a READ command, as shown in Figure 11. The ...
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Figure 11: READ Command A0–A8 A9, A11, A12 BA0, BA1 Notes enable auto precharge DIS AP = disable auto precharge Upon completion of a burst, assuming no other commands have been initiated, the DQs will go ...
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Figure 12: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Each READ command may be to any bank. DQM is LOW. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 ...
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Figure 13: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on page 26 shows the case where the clock frequency ...
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Figure 15: READ-to-WRITE with Extra Clock Cycle DQM COMMAND ADDRESS Notes The READ command may be to any bank, and the WRITE command may be to any bank. Figure 16: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Notes: ...
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Fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...
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WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 21 on page 32, or each subsequent WRITE may be performed to a different bank. Figure 19: WRITE Burst CLK ...
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In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same opera- tion that would result from the same fixed-length burst with auto precharge. The disad- ...
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Figure 23: WRITE-to-PRECHARGE t t WR@ DQM COMMAND ADDRESS t t WR@ DQM COMMAND ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Figure 24: Terminating a WRITE Burst ...
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Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that ...
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... Deep Power-Down Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data on the memory array will not be retained once deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...
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Figure 28: Deep Power-Down T0 CK CKE COMMAND NOP All Banks idle with no activity on the data bus Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = Deep power-down mode command; PRE ALL = ...
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Figure 29: Clock Suspend During WRITE Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Notes: 1. For this example greater, and DQM is LOW. Figure 30: Clock Suspend During READ Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS ...
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Concurrent Auto Precharge An access command (READ or WRITE second bank while an access command with auto precharge enabled on a first bank is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron ...
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Figure 32: READ With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS Notes: 1. DQM is HIGH prevent D PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg ...
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WRITE with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n ...
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Truth Tables Table 6: Truth Table – CKE Notes: 1–4 CKE CKE Current State n Power-Down Self refresh Clock suspend Deep power-down L H Power-Down Deep power-down Self refresh Clock suspend H L All banks idle All ...
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Table 7: Truth Table – Current State Bank n, Command to Bank n Notes: 1–6; notes appear below table Current State CS# RAS# CAS# Any Idle Row active ...
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The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not ...
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Table 8: Truth Table – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# CAS# Any Idle X X Row L L activating, L ...
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A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those ...
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Table 11: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on pages 51–52 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level ...
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Table 12: AC Functional Characteristics Notes 9,11; notes appear on pages 51–52 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit mode DQM to input ...
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Table 13: I Specifications and Conditions (x16) DD Notes 11, 13; notes appear on pages 51–52; V Parameter/Condition Operating current: Active mode; Burst = 1; READ or WRITE; Standby current: Power-down mode; All banks idle; CKE = ...
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Table 15 Specifications and Conditions (x16 and x32) DD Notes:1–6, 8, 11, 13, 15, 27; notes appear on pages 51–52; V Parameter/Condition Self refresh t t CKE = LOW (MIN); Address and control inputs are ...
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Table 16: Capacitance (x16) Note: 2; notes appear on pages 51–52 Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/Output capacitance: DQs Table 17: Capacitance (x32) Note: 2; notes appear on pages 51–52 Parameter Input capacitance: CLK Input ...
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Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid V 13 14. Timing actually specified by cycle rate. 15. Timing actually specified by minimum cycle rate. 16. ...
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Timing Diagrams Figure 36: Initialize and Load Mode Register CLK ( ( ) ) t t CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) ...
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Figure 37: Power-Down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all ...
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Figure 38: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM A0–A9, 2 COLUMN ...
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Figure 39: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...
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Figure 40: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High ...
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Figure 41: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ROW ADDR ROW A10 DISABLE ...
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Figure 42: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 ...
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Figure 43: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 DISABLE AUTO ...
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Figure 44: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 ...
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Figure 45: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ROW ADDR ENABLE AUTO ...
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Figure 46: READ – Continuous-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ADDR ROW COLUMN m t ...
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Figure 47: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ENABLE AUTO PRECHARGE ROW A10 DISABLE ...
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Figure 48: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ADDR ROW COLUMN ...
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Figure 49: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ADDR ROW COLUMN ...
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Figure 50: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 DISABLE AUTO ...
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Figure 51: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ROW ADDR ROW A10 ...
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Figure 52: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM ROW ADDR COLUMN ...
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Figure 53: WRITE – Continuous-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ADDR ROW ROW A10 t AS ...
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Figure 54: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM ADDR ROW ROW A10 ...
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Package Dimensions Figure 55: 54-Ball VFBGA (10mm x 11.5mm) Seating plane 0 ±0.10 54X Ø0.45 Dimensions apply to solder balls post reflow Pre-reflow balls are Ø0.42 on Ø0.40 SMD ball pads. 3.2 6.4 0.8 ...
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Figure 56: 90-Ball VFBGA (10mm x 13mm) Seating plane A 0.1 A 90X Ø0.45 Dimensions apply 10 ±0.1 to solder balls post reflow. The pre- reflow balls are Ø0.42 on Ø0. SMD ball pads. 5.6 11.2 0.8 ...