MT41J256M8JE-15E:A Micron Technology Inc, MT41J256M8JE-15E:A Datasheet
MT41J256M8JE-15E:A
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MT41J256M8JE-15E:A Summary of contents
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DDR3 SDRAM MT41J512M4 – 64 Meg Banks MT41J256M8 – 32 Meg Banks MT41J128M16 – 16 Meg Banks Features • +1.5V ±0.075V DD DD ...
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Table 2: Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Figure 1: 2Gb DDR3 Part Numbers Package 78-ball 9mm x 11.5mm FBGA 82-ball 12.5mm x 15.5mm FBGA 96-ball 9mm x 14mm FBGA Notes: 1. Not all options ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 2Gb DDR3 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 57: Mode Register 3 (MR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 113: Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 52: DDR3-800 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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State Diagram Figure 2: Simplified State Diagram Power applied Reset Power procedure on From any RESET state ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE ...
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Functional Description The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ...
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Any specific requirement takes precedence over a general statement. • Any functionality not specifically stated herewithin is considered undefined, illegal, and not supported and can result in unknown operation. • Row addressing is denoted as A[n:0](2Gb ...
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... Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory internally configured as an 8-bank DRAM. Figure 3: 512 Meg x 4 Functional Block Diagram ODT ZQ RESET# RZQ ZQCL, ZQCS CKE Control A12 logic CK, CK# BC4 (burst chop) CS# RAS# OTF CAS# WE# ...
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... Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 Bank 0 Bank 0 Row- 14 memory row- address array address MUX 16,384 (16,384 x 128 x 128) latch and decoder Sense amplifiers 128 16,384 BC4 OTF I/O gating 3 DM mask logic ...
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Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View Notes: 1. Ball descriptions listed in Table 3 on page 18 are ...
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Figure 7: 82-Ball FBGA – x4, x8 Pin Assignments (Top View Notes: 1. Ball descriptions are listed Table 4 on page 20 as “x4, x8” if unique, ...
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Figure 8: 96-Ball FBGA – x16 Ball Assignments (Top View Notes: 1. Ball descriptions listed in Table 5 on page 22 are listed as ...
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... Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH) ...
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Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (continued) Ball Assignments Symbol N2 RESET# B3, C7, DQ0, DQ1, C2, C8 DQ2, DQ3 B3, C7, C2, DQ0, DQ1, DQ2, C8, E3, E8, DQ3, DQ4, DQ5, D2, E7 DQ6, DQ7 C3, ...
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... Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH) ...
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Table 4: 82-Ball FBGA (x4, x8) (continued) Ball Number Symbol N3 RESET# B4, C8, DQ0, DQ1, C3, C9 DQ2, DQ3 B4, C8, C3, DQ0, DQ1, DQ2, C9, E4, E9, DQ3, DQ4, DQ5, D3, E8 DQ6, DQ7 C4, D4 DQS, DQS# ...
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... Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH) ...
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Table 5: 96-Ball FBGA – x16 Ball Descriptions (continued) Ball Assignments Symbol T2 RESET# D3 UDM E3, F7, F2, DQ0, DQ1, DQ2, F8, H3, H8, DQ3, DQ4, DQ5, G2, H7 DQ6, DQ7 D7, C3, DQ8, DQ9, C8, C2, DQ10, DQ11, ...
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Package Dimensions Figure 9: 78-Ball FBGA – x4, x8; “HX” Seating plane A 0.12 A 78X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post reflow on Ø0.33 NSMD ball pads. 9.6 CTR 0.8 TYP ...
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Figure 10: 82-Ball FBGA – x4, x8; “JE“ Seating plane A 0.12 A 82X Ø0.45 Solder ball material: SAC305. Dimensions apply solder balls post-reflow on Ø0.33 NSMD ball pads. 0.8 TYP 9.6 CTR 0.8 TYP ...
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Figure 11: 96-Ball FBGA – x16; “HA“ Seating plane A 0.12 A 96X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow Ø0.4 SMD ball pads. 12 CTR 0.8 TYP 0.8 TYP 6.4 CTR ...
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Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated ...
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Thermal Characteristics Table 8: Thermal Characteristics Parameter/Condition Operating case temperature Junction-to-case (TOP) Notes: 1. MAX operating case temperature. T Figure 12 thermal solution must be designed to ensure the DRAM device does not exceed the maxi- mum T ...
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Electrical Specifications – I Within the following Idd measurement tables (Table 9 through Table 19), the following definitions and conditions are used, unless stated otherwise: • LOW: V • Mid-level: Inputs are V • • • ...
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Table 10 Measurement Loop nRAS 0 nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRAS 2 × nRC 1 4 × nRC 2 6 × ...
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Table 11 Measurement Loop nRCD nRAS 0 nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRCD nRC + nRAS 2 × nRC 1 4 × ...
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Table 12 Measurement Conditions for Power-Down Currents Name Timing pattern CKE External clock RAS t RCD t RRD CS# Command inputs Row/column addr Bank addresses DM ...
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Table 13 and I 3N Measurement Loop 4–7 1 8–11 2 12–15 3 16–19 4 20–23 5 24–27 6 28–31 7 Notes: 1. DQs, DQS, DQS# are mid-level ...
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Table 15 Measurement Loop 8–15 1 16–23 2 24–31 3 32–39 4 40–47 5 48–55 6 56–63 7 Notes: 1. DQs, DQS, DQS# are mid-level when not driving ...
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Table 16 Measurement Loop 8–15 1 16–23 2 24–31 3 32–39 4 40–47 5 48–55 6 56–63 7 Notes: 1. DQs, DQS, DQS# are mid-level when not driving ...
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Table 17 Measurement Loop 5–8 1b 9–12 1c 13–16 1d 17–20 1e 21–24 1f 25–28 1g 29–32 1h 33–nRFC - 1 2 Notes: 1. DQs, DQS, DQS# are mid-level. 2. ...
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Table 18: I Measurement Conditions for Test DD Active banks Idle banks SRT ASR Notes: 1. Enabled, mid-level“ means the MR command is enabled, but the signal is mid-level. 2. During a cold boot RESET ...
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Table 19 Measurement Loop nRRD nRRD + 1 nRRD + 2 nRRD + × nRRD 3 3 × nRRD 4 4 × nRRD 4 × nRRD + 1 ...
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Electrical Characteristics – values are for full operating range of voltage and temperature unless otherwise DD noted. Table 20: I Maximum Limits - Die Rev A DD Speed Bin I Width DDR3-800 ...
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Table 21: I Maximum Limits - Die Rev D DD Speed Bin I Width DDR3-800 x16 x16 115 I 2P0 (slow) All 12 DD ...
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Table 22: I Maximum Limits - Die Rev F DD Speed Bin I Width DDR3-800 2P0 (slow) All 2P1 (fast) All ...
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Electrical Specifications – DC and AC DC Operating Conditions Table 23: DC Electrical Characteristics and Operating Conditions All voltages are referenced to V Parameter/Condition Supply voltage I/O supply voltage Input leakage current Any input 0V ≤ V ≤ V pin ...
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Table 25: Input Switching Conditions Parameter/Condition Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: ...
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Figure 13: Input Signal Minimum V and V levels 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V ...
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Table 27: Clock, Data, Strobe, and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 14 on page 45) Maximum peak amplitude allowed for undershoot area (see Figure 15 on page 45) Maximum overshoot area above V ...
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Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Differential input voltage logic high - slew Differential input voltage logic low - slew Differential input voltage logic high Differential input voltage logic low Differential input crossing voltage ...
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Figure 17: Single-Ended Requirements for Differential Signals PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/ (MIN) SEH Q SEH (MAX) SEL or V ...
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Figure 18: Definition of Differential AC-Swing and V ( IHDIFF V IHDIFF V ( IHDIFF V ( ILDIFF DC V ILDIFF V ( ILDIFF AC Table 29: Allowed Time Before Ringback ( Below PDF: 09005aef826aaadc/Source: ...
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Slew Rate Definitions for Single-Ended Input Signals Setup ( between the last crossing DS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V Hold ( between the ...
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Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Electrical Specifications – DC and AC ΔTFS ΔTRH ΔTFH Micron Technology, Inc., reserves the right to change products or ...
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Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 31 and Figure 20. The nominal slew rate for a rising signal is defined ...
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ODT Characteristics ODT effective resistance R DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values are listed in Table 32 and Table 33 on page 53. A functional representation of the ODT is shown in ...
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Table 33: R Effective Impedances TT MR1 [ Resistor 120Ω 120PD240 R TT 120PU240 120Ω 60Ω 60PD120 R TT 60PU120 60Ω 40Ω R ...
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Table 34: ODT Sensitivity Definition Symbol Min R 0 × |DT Δ T(@ calibration), Δ Notes: Table 35: ODT Temperature and Voltage Sensitivity 1. Δ ...
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Table 37: Reference Settings for ODT Timing Measurements Measured Parameter AON t AOF t AONPD t AOFPD t ADC Notes: 1. Assume an RZQ of 240Ω (±1%) and that proper ZQ calibration has been performed at a ...
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Figure 24: AONPD and AOFPD Definition t AONPD Begin point: Rising edge CK# with ODT first registered HIGH CK CK# DQ, DM DQS, DQS# TDQS, TDQS Figure 25: ADC Definition Begin ...
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Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically ...
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Table 38: 34Ω Driver Impedance Characteristics MR1[5,1] R Resistor ON 0,1 34.3Ω 34PD R ON 34PU Pull-up/pull-down mismatch (MM Notes: 1. Tolerance limits assume RZQ of 240Ω (±1%) and are applicable after proper ZQ calibration has been performed ...
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Table 40: 34Ω Driver MR1[5,1] R Resistor 34.3Ω 34PD R ON 34PU Table 41: 34Ω Driver MR1[5,1] R Resistor 34.3Ω 34PD R ...
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Table 44: 34Ω Output Driver Voltage and Temperature Sensitivity Alternative 40 Ohm Driver Table 45: 40Ω Driver Impedance Characteristics MR1[5,1] R Resistor ON 0,0 40Ω 40PD R ON 40PU Pull-up/pull-down mismatch (MM Notes: 1. Tolerance limits assume RZQ ...
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Table 47: 40Ω Output Driver Voltage and Temperature Sensitivity Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 48 while the differential output driver is summa- rized ...
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Table 49: Differential Output Driver Characteristics All voltages are referenced to Vss Parameter/Condition Output leakage current: DQ are disabled; 0V ≤ V ≤ ODT is disabled; ODT is HIGH OUT DD Output slew rate: Differential; For rising and ...
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Figure 28: Differential Output Signal X Reference Output Load Figure 29 represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It ...
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Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 48 on page 61. With the refer- ence load for timing measurements, the output slew rate for falling and rising edges is defined and measured ...
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Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 49 on page 62. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between ...
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Speed Bin Tables Table 52: DDR3-800 Speed Bins DDR3-800 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL ...
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Table 53: DDR3-1066 Speed Bins DDR3-1066 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
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Table 54: DDR3-1333 Speed Bins DDR3-1333 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
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Table 55: DDR3-1600 Speed Bins DDR3-1600 Speed Bin t t CL- RCD- RP Parameter ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL = 5 CWL ...
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Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C ...
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Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data setup ...
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Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter DLL locking time CTRL, CMD, ADDR Base (specification) setup to CK,CK V/ns ...
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Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter ZQCL command: Long POWER-UP and RESET calibration time operation Normal operation ZQCS command: Short calibration ...
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Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin ...
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Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter R synchronous turn-on delay TT R synchronous turn-off delay TT R turn-on from ODTL on ...
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Notes 1. Parameters are applicable with 0°C 2. All voltages are referenced Output timings are only valid for R 4. Unit “ Unit “CK” represents one clock cycle of the input clock, counting the actual clock edges. ...
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The cumulative jitter error ( 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. t 18. DS (base) and 2 V/ns differential DQS, DQS# slew rate. ...
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The start of the write recovery time is defined as follows: – For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL – For BC4 (OTF): Rising clock edge four clock cycles after WL ...
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Command and Address Setup, Hold, and Derating The total sheet page 70) to the Δ page 80), respectively. Example: sition, the input signal has to remain above/below V (see Table 59 on page 80). Although the total setup time for ...
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Table 58: Derating Values for AC175 Threshold: V CMD/ ADDR 4.0 V/ns 3.0 V/ns Slew Rate Δ t Δ t Δ 0.9 –2 ...
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Table 60: Minimum Required Time Below PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/ VAC Above for Valid Transition Slew Rate (V/ns) VAC at 175mV (ps) >2.0 ...
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Figure 32: Nominal Slew Rate and CK CK# DQS# DQS MIN MIN REF MAX ...
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Figure 33: Nominal Slew Rate for CK CK# DQS# DQS MIN MIN region REF MAX IL DC ...
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Figure 34: Tangent Line for CK CK# DQS# DQS MIN REF region MIN REF MAX ...
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Figure 35: Tangent Line for CK CK# DQS# DQS MIN MIN region REF region ...
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Data Setup, Hold, and Derating The total sheet page 70) to the Δ Example: signal has to remain above/below V page 88). Although the total setup time for slow slew rates might be negative (for example, a valid input signal ...
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Table 62: Derating Values for Shaded cells indicate slew rate combinations not supported 4.0 V/ns 3.0 V/ns DQ Slew Δ Δ Δ Δ Rate V/ 1.0 ...
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Table 64: Required Time VAC Above V PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/ (Below VAC at 175mV (ps) Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 ...
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Figure 36: Nominal Slew Rate and CK CK# DQS# DQS MIN REF MIN REF MAX ...
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Figure 37: Nominal Slew Rate for CK CK# DQS# DQS MIN MIN region REF MAX IL DC ...
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Figure 38: Tangent Line for CK CK# DQS# DQS MIN REF region MIN REF MAX ...
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Figure 39: Tangent Line for CK CK# DQS# DQS MIN MIN region REF region ...
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Commands Truth Tables Table 65: Truth Table – Command Notes 1–5 apply to the entire table Function Symbol MODE REGISTER SET MRS REFRESH REF Self refresh entry SRE Self refresh exit SRX Single-bank PRECHARGE PRE PRECHARGE all banks PREA Bank ...
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Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.” 6. See Table 66 for ...
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NO OPERATION (NOP) The NOP command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ CALIBRATION LONG (ZQCL) The ZQCL command is used to perform the ...
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... WRITE command is issued determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 68. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location ...
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However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH ...
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The second REFRESH is not required but depicts two back-to-back REFRESH commands. 3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks). ...
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After 4. Self refresh may be exited when the clock is stable with the new frequency for After 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of appropriate timings ...
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Figure 42: DLL Disable Mode to DLL Enable Mode T0 Ta0 Ta1 CK# CK CKE SRE 1 Command NOP NOP t CKSRE 7 ODTL off + 1 × ODT 10 Notes: 1. Enter SELF REFRESH. 2. Exit SELF ...
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Figure 43: DLL Disable DQSCK Timing T0 T1 CK# CK READ NOP Command Valid Address DQS, DQS# DLL on DQ BL8 DLL on RL (DLL disable ( DQS, DQS# DLL off DQ ...
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DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time NOM ready to operate with a new clock ...
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... For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required ...
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When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK’s status. The prime DQ for configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The ...
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... NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12 “1” in the other ranks. The memory controller may assert ODT after a ODT transition ...
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... After the last rising DQS (capturing a “1” at T0), the memory controller should stop driving the DQS signals after the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until t MOD after the MRS command (at Te1) ...
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Figure 47: Exit Write Leveling T0 T1 CK# CK Command NOP NOP Address ODT R DQS, R DQS DQS, DQS# R _DQ TT t WLO + t WLOE DQ Notes: 1. The DQ result, “= 1,” between ...
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Operations Initialization The following sequence is required for power up and initialization, as shown in Figure 48 on page 109: 1. Apply power. RESET# is recommended to be below 0.2 × V ensure the outputs remain disabled (High-Z) and ODT ...
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Figure 48: Initialization Sequence T (MAX) = 200ms V DD See power-up conditions in the initialization sequence text, V set REF Power-up t VTD ramp CK 20ns RESET# ...
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... MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or reissued) when all banks are idle and in the ...
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Figure 50: MRS-to-nonMRS Command Timing ( CK# Command Address CKE Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, must be satisfied, and no data bursts can be in progress). 2. Prior ...
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Figure 51: Mode Register 0 (MR0) Definitions M15 M14 Mode Register 0 0 Mode register 0 (MR0 Mode register 1 (MR1 Mode register 2 (MR2 Mode register 3 (MR3) Notes: 1. MR0[16, 13, 7, ...
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Table 71: Burst Order Starting Column Burst READ/ Address Length WRITE (A[2, 1, 0]) 4 chop READ ...
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Precharge Power-Down (Precharge PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a lower standby current mode; however, MR0[12] is set ...
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... RESET# goes LOW, or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. ...
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The DRAM is not tested to check—nor does Micron warrant compliance with—normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the ...
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... The actual effective termination, R nonlinearity of the termination. For R Termination (ODT)” on page 161). The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when R on) and off (ODTL off ), assuming ODT has been enabled via MR1[9, 6, 2]. Timings for ODT are detailed in “ ...
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... MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time quent operation ...
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CAS Write Latency (CWL) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corre- sponding ...
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SRT vs. ASR If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of 95°C is needed, the user ...
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... LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller ...
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... A predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command ...
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A11 is a “Don’t Care” • A12: Selects burst chop mode on-the-fly, if enabled within MR0 • A13 is a “Don’t Care” • BA[2:0] are a “Don’t Care” MPR Register Address Definitions and Bursting Order The MPR currently supports ...
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... Valid A10/ Valid A11 0 Valid Valid 1 A12/BC# 0 A[15:13] 0 Valid DQS, DQS# DQ Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Tc0 Tc1 Tc2 Tc3 Tc4 NOP NOP NOP NOP NOP RL Tc5 Tc6 Tc7 Tc8 Tc9 NOP NOP ...
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... Valid A11 0 Valid Valid Valid 1 A12/BC# 0 Valid A[15:13] 0 Valid Valid RL DQS, DQS# DQ Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Tc1 Tc2 Tc3 Tc4 Tc5 NOP NOP NOP NOP NOP RL Tc6 Tc7 Tc8 Tc9 Tc10 NOP ...
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... Valid Valid 1 Valid 1 A12/BC# 0 A[15:13] 0 Valid Valid RL DQS, DQS# DQ Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0 selects lower 4 nibble bits selects upper 4 nibble bits Tc1 Tc2 Tc3 Tc4 Tc5 NOP NOP NOP NOP NOP RL Tc6 ...
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... Valid Valid 1 Valid 1 A12/BC# 0 A[15:13] 0 Valid Valid RL DQS, DQS# DQ Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0 selects upper 4 nibble bits selects lower 4 nibble bits Tc1 Tc2 Tc3 Tc4 Tc5 NOP NOP NOP NOP NOP RL Tc6 ...
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... DRAM array • When (such as activate a memory bank for regular read or write access) are permitted MODE REGISTER SET (MRS) The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode register is programmed: • ...
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DDR3 SDRAM need a longer time to calibrate R and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example ...
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ACTIVATE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. ...
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READ READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row ...
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Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 70 on page 134 (BC4 is shown in ...
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Figure 67: Consecutive READ Bursts (BL8 CK# CK Command 1 READ NOP NOP NOP t CCD Bank, Address 2 Col n DQS, DQS Notes: 1. NOP commands are shown for ease ...
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Figure 69: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS# DQ Notes ...
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Figure 71: READ (BC4) to WRITE (BC4) OTF CK# CK Command 1 READ NOP NOP NOP READ-to-WRITE command delay = CCD Bank, Address 2 Col n DQS, ...
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Figure 73: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 74: READ to PRECHARGE ( ...
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A DQS to DQ output timing is shown in Figure 76 on page 138. The DQ transitions between valid data outputs must be within DQS must also maintain a minimum HIGH and LOW time of READ preamble, the DQ balls ...
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Figure 76: Data Output Timing – DQSQ and Data Valid Window T0 T1 CK# CK Command 1 READ NOP Bank, Address 2 Col n DQS, DQS (last data valid (first data no longer valid) All ...
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HZ and parameters are referenced to a specific voltage level which specifies when the device output is no longer driving t LZ (DQ). Figure 78 shows a method to calculate the point when the device is no longer driving ...
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Figure 79: RPRE Timing CK CK# DQS Single-ended signal provided as background information DQS# Single-ended signal provided as background information DQS - DQS# Resulting differential signal relevant for t RPRE specification t Figure 80: RPST Timing DQS Single-ended signal, ...
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WRITE WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being ...
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Figure 81: WPRE Timing CK CK# DQS - DQS# Resulting differential t Figure 82: WPST Timing CK CK# DQS - DQS# Resulting differential signal relevant for t WPST specification PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/ ...
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Figure 83: Write Burst CK# CK Command 1 WRITE NOP NOP CWL Bank, Address 2 Col n t DQSS (MIN) DQS, DQS DQSS (NOM) DQS, DQS DQSS ...
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Figure 84: Consecutive WRITE (BL8) to WRITE (BL8 CK# CK Command 1 WRITE NOP NOP NOP t CCD Address 2 Valid DQS, DQS Notes: 1. NOP commands are shown for ease ...
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Figure 86: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...
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Figure 88: WRITE to READ (BC4 Mode Register Setting CK# CK Command 1 WRITE NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of illustration; other commands may be ...
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Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF CK# CK Command 1 WRITE NOP NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of ...
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Figure 90: WRITE (BL8) to PRECHARGE CK# CK Command WRITE NOP NOP NOP Valid Address CWL DQS, DQS# DQ BL8 Notes data-in from column n. 2. Seven subsequent ...
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Figure 92: WRITE (BC4 OTF) to PRECHARGE CK# CK Command 1 WRITE NOP NOP Bank, Address 3 Col n DQS, DQS Notes: 1. NOP commands are shown for ease of illustration; other commands may be ...
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PRECHARGE Input A10 determines whether one bank or all banks are to be precharged, and in the case where only one bank precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs BA[2:0] ...
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Figure 94: Self Refresh Entry/Exit Timing CK CKSRE CPDED CKE t IS ODT 2 RESET# 2 SRE (REF) 3 NOP 4 Command NOP Address Enter self refresh mode ...
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Extended Temperature Usage Micron’s DDR3 SDRAM support the optional extended temperature range of 0°C to 95° Thus, the SRT and ASR options must be used at a minimum. C The extended temperature range DRAM must be refreshed externally ...
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Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is ...
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While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must valid state but all other input signals are a “Don’t Care.” If RESET# goes ...
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Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit Command NOP t IS CKE Enter power-down mode Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ...
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Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP Ta0 Ta1 CK# CK READ/ NOP NOP NOP Command RDAP CKE Address Valid DQS, DQS# DQ BL8 DQ BC4 Figure 99: ...
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Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP Ta0 Ta1 CK# CK WRAP NOP NOP NOP Command CKE Address Valid A10 CWL DQS, DQS# DQ BL8 DQ BC4 t Notes ...
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Figure 102: ACTIVATE to Power-Down Entry Command ACTIVE Address Valid CKE t ACTPDEN Figure 103: PRECHARGE to Power-Down Entry Command PRE All/single Address bank ...
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Figure 104: MRS Command to Power-Down Entry Command MRS NOP Address Valid CKE Figure 105: Power-Down Exit to Refresh to Power-Down Entry Command NOP ...
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Figure 106: RESET Sequence System RESET (warm boot) Stable and valid clock CK (MIN) = MAX (10ns CK 100ns (MIN) t IOZ RESET# T=10ns (MIN) CKE ODT Command DM Address A10 BA[2:0] High-Z DQS ...
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... TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. The ODT feature is designed to improve signal integrity of the memory channel by enabling the DRAM controller to independently turn on/off the DRAM’s internal termi- nation resistance for any grouping of DRAM devices ...
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Table 78: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[ ODT Pin 000 0 000 1 000–101 0 000–101 1 110 and 111 X Notes: 1. Assumes dynamic ODT is disabled (see “Dynamic ...
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Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination ...
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Table 81: Mode Registers for R MR1 ( NOM Notes: 1. RZQ = 240Ω Table 82: ...
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Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 Address Valid ODTH4 ODT ODTL DQS, DQS# DQ Notes: 1. Via MRS ...
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Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTL CNW Address Valid ODTL ON ODT R TT DQS, DQS# DQ Notes: 1. Via ...
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Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 CK# CK Command NOP WRS4 NOP ODTL Address Valid ODT ODTL DQS, DQS# DQ Notes: 1. Via MRS or ...
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Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either R modes are: • Any bank active with CKE HIGH • Refresh mode with CKE HIGH • Idle mode with CKE ...
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Table 84: Synchronous ODT Parameters Symbol Description ODTL on ODT synchronous turn-on delay ODTL off ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ...
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Figure 114: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTL Notes NOM 2. ODT ...
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ODT Off During READs As the DDR3 SDRAM cannot terminate and drive at the same time least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R amble as shown in the ...
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Figure 115: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTL off = CWL + ODT DQS, DQS# DQ Notes: 1. ODT must be ...
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Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either R precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchro- nously when the DLL is synchronizing after being reset. See “Power-Down ...
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Figure 116: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Notes ignored. Table 85: Asynchronous ODT Timing Parameters for All ...
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Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off ...
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Table 86: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Power-down entry transition period (power-down entry) Power-down exit transition period (power-down exit) ODT to R turn-on delay (ODTL ODT to ...
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Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by ...
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Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit Ta0 Ta1 CK# CK CKE COMMAND NOP t ANPD ODT A asynchronous t AOFPD (MIN) DRAM NOM asynchronous t ...
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Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, ...
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Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping CK# CK Command REF NOP NOP NOP CKE t ANPD Short CKE LOW transition period (R Notes ...
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