IC SRAM 1MBIT 12NS 44SOJ

 

CY7C1021BV33-12VC

Manufacturer Part NumberCY7C1021BV33-12VC
DescriptionIC SRAM 1MBIT 12NS 44SOJ
ManufacturerCypress Semiconductor Corp
CY7C1021BV33-12VC datasheets

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Specifications of CY7C1021BV33-12VC

Format - MemoryRAMMemory TypeSRAM - Asynchronous
Memory Size1M (64K x 16)Speed12ns
InterfaceParallelVoltage - Supply3 V ~ 3.6 V
Operating Temperature0°C ~ 70°CPackage / Case44-SOJ
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names428-1014
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Features
• 3.3V operation (3.0V–3.6V)
• High speed
— t
= 10/12/15 ns
AA
• CMOS for optimum speed/power
• Low Active Power (L version)
— 576 mW (max.)
• Low CMOS Standby Power (L version)
— 1.80 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
• Available in a 48-Ball Mini BGA package
[1]
Functional Description
The CY7C1021BV is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an au-
tomatic power-down feature that significantly reduces power
consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
64K x 16
5
A
4
RAM Array
A
512 X 2048
3
A
2
A
1
A
0
COLUMN DECODER
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current
(mA)
Shaded areas contain advance information.
Note:
1.
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05148 Rev. *A
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and
BLE are disabled (BHE, BLE HIGH), or during a write opera-
tion (CE LOW, and WE LOW).
The CY7C1021BV is available in 400-mil-wide SOJ, standard
44-pin TSOP Type II, and 48-ball mini BGA packages.
I/O
I/O
7C1021BV-8
8
Commercial
170
Industrial
190
Commercial
5
L
0.500
•
3901 North First Street
•
CY7C1021BV33
64K x 16 Static RAM
through I/O
1
). If Byte High Enable (BHE) is LOW, then data
15
through I/O
) is written into the location
9
16
through A
).
0
15
to I/O
. If Byte High Enable (BHE) is LOW,
1
8
to I/O
9
through I/O
) are placed in a
1
16
Pin Configurations
SOJ / TSOP II
Top View
A
44
A 5
1
4
A 3
A 6
43
2
A 2
42
3
A 7
A 1
OE
4
41
40
A 0
BHE
5
39
BLE
CE
6
–I/O
38
I/O 1
I/O 16
1
8
7
37
I/O 2
I/O 15
8
–I/O
I/O 3
36
I/O 14
9
9
16
35
I/O 4
10
I/O 13
V
34
V
11
SS
CC
V
33
V
12
SS
CC
I/O 5
I/O 12
32
13
I/O 6
I/O 11
31
14
I/O 7
I/O 10
30
15
I/O 8
I/O 9
29
16
WE
28
NC
17
A 8
A 15
18
27
BHE
A 14
A 9
19
26
WE
A 13
A 10
20
25
CE
A 11
A 12
21
24
OE
NC
NC
22
23
BLE
7C1021BV-10
7C1021BV-12
7C1021BV-15
10
12
160
150
180
170
5
5
0.500
0.500
San Jose
•
CA 95134
•
408-943-2600
Revised September 13, 2002
), is
8
0
See the
16 .
15
140
160
5
0.500

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CY7C1021BV33-12VC Summary of contents

  • Page 1

    ... I/O I/O 7C1021BV-8 8 Commercial 170 Industrial 190 Commercial 5 L 0.500 • 3901 North First Street • CY7C1021BV33 64K x 16 Static RAM through I Byte High Enable (BHE) is LOW, then data 15 through I written into the location 9 16 through I Byte High Enable (BHE) is LOW, ...

  • Page 2

    ... I/O I Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range [2] Range .... –0.5V to +4.6V Commercial +0.5V CC Industrial +0.5V CC CY7C1021BV33 Ambient Temperature V CC 0°C to +70°C 3.3V –40°C to +85°C 3.3V Page 10% 10% ...

  • Page 3

    ... CC < 0.3V, Test Conditions T = 25° MHz A R 317 3.3V 3.0V R2 GND 5 pF 351 INCLUDING JIG AND Rise Time: 1 V/ns SCOPE (b) 167 1.73V 30 pF CY7C1021BV33 7C1021BV-12 7C1021BV-15 Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0 0.3V 0.3V ...

  • Page 4

    ... Min. Max. Min Over the Operating Range (L version only) Conditions Com’ 2.0V > V – 0.3V > V – 0. less than less than t HZCE LZCE HZOE CY7C1021BV33 7C1021BV-12 7C1021BV-15 Max. Min. Max. Min [8] Min. Max. 2.0 100 < 0. and t is less than t for any given device ...

  • Page 5

    ... WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05148 Rev. *A DATA RETENTION MODE 3.0V > CDR OHA [12, 13 ACE t DOE t LZOE t DBE t LZBE 50 CY7C1021BV33 3. DATA VALID t HZOE t HZCE t HZBE IMPEDANCE DATA VALID t PD 50% HIGH I ICC CC I ISB SB Page ...

  • Page 6

    ... Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATA I/O Notes: 14. Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05148 Rev. *A [14, 15 SCE PWE PWE t SCE . IH CY7C1021BV33 Page ...

  • Page 7

    ... High Z Read - Lower bits only Data Out Read - Upper bits only Data In Write - All bits High Z Write - Lower bits only Data In Write - Upper bits only High Z Selected, Outputs Disabled High Z Selected, Outputs Disabled CY7C1021BV33 LZWE Mode Power Standby (I Active (I CC Active (I ...

  • Page 8

    ... Ordering Information Speed (ns) Ordering Code 8 CY7C1021BV33-8BAC CY7C1021BV33-8VC CY7C1021BV33L-8VC CY7C1021BV33-8ZC CY7C1021BV33L-8ZC 10 CY7C1021BV33-10BAC CY7C1021BV33-10VC CY7C1021BV33L-10VC CY7C1021BV33-10ZC CY7C1021BV33L-10ZC 12 CY7C1021BV33-12BAC CY7C1021BV33-12VC CY7C1021BV33L-12VC CY7C1021BV33-12ZC CY7C1021BV33L-12ZC CY7C1021BV33-12BAI CY7C1021BV33-12VI 15 CY7C1021BV33-15BAC CY7C1021BV33L-15BAC CY7C1021BV33-15VC CY7C1021BV33L-15VC CY7C1021BV33-15ZC CY7C1021BV33L-15VC CY7C1021BV33-15BAI CY7C1021BV33L-15BAI CY7C1021BV33-15VI CY7C1021BV33L-15ZI Shaded areas contain advance information. Document #: 38-05148 Rev. *A Package ...

  • Page 9

    ... Package Diagrams 48-Ball (7. 7. 1.2 mm) FBGA BA48A Document #: 38-05148 Rev. *A CY7C1021BV33 51-85096-*E Page ...

  • Page 10

    ... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 44-Lead (400-Mil) Molded SOJ V34 44-Pin TSOP II Z44 CY7C1021BV33 51-85082-*B 51-85087-A Page ...

  • Page 11

    ... Document History Page Document Title: CY7C1021BV33 64K x 16 Static RAM Document Number: 38-05148 Issue REV. ECN NO. Date ** 109892 09/22/01 *A 116474 09/16/02 Document #: 38-05148 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00954 to 38-05148 CEA Add applications foot note to data sheet, page 1. ...

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