Features
• High speed
— t
= 12 ns
AA
• Low active power
— 495 mW (max. 12 ns)
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
Functional Description
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy mem-
ory expansion is provided by an active LOW Chip Enable
(CE
), an active HIGH Chip Enable (CE
1
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
512 x 256 x 8
A
5
ARRAY
A
6
A
7
A
8
COLUMN
CE
1
DECODER
CE
2
WE
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
Cypress Semiconductor Corporation
Document #: 38-05038 Rev. **
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE
Enable (WE) inputs LOW and Chip Enable Two (CE
HIGH. Data on the eight I/O pins (I/O
written into the location specified on the address pins (A
through A
Reading from the device is accomplished by taking Chip En-
able One (CE
Write Enable (WE) and Chip Enable Two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
, CE
, and OE options
1
2
HIGH or CE
during a write operation (CE
The CY7C109B is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009B is available in
a 300-mil-wide SOJ package. The CY7C1009B and
CY7C109B are functionally equivalent in all other respects.
), an active LOW Out-
2
I/O
0
I/O
1
I/O
2
A
I/O
11
3
A
9
A
8
I/O
A
13
4
WE
CE
2
I/O
A
5
15
V
CC
NC
I/O
A
6
16
POWER
A
DOWN
14
A
12
I/O
A
7
7
A
6
A
109B–1
5
A
4
7C109B-12
7C109B-15
7C1009B-12
7C1009B-15
12
15
90
80
10
10
2
2
•
3901 North First Street
•
CY7C109B
CY7C1009B
128K x 8 Static RAM
through I/O
0
).
16
) and Output Enable (OE) LOW while forcing
1
) HIGH. Under
2
through I/O
) are placed in a
0
7
LOW), the outputs are disabled (OE HIGH), or
2
LOW, CE
HIGH, and WE LOW).
1
2
Pin Configurations
SOJ
Top View
NC
V
32
1
CC
A
31
A
2
16
15
A
30
3
CE
14
2
A
4
29
WE
12
28
5
A
A
7
13
27
A
6
A
6
8
26
A
7
A
5
9
25
A
8
A
4
11
24
A
9
3
OE
A
23
A
10
2
10
A
22
CE
1
11
1
I/O
21
A
12
7
0
I/O
I/O
0
13
20
6
I/O
I/O
19
1
14
5
I/O
I/O
15
18
2
4
GND
17
I/O
16
3
109B–2
1
2
3
4
5
6
7
TSOP I
8
Top View
(not to scale)
9
10
11
12
13
14
15
16
7C109B-20
7C109B-25
7C109B-35
7C1009B-20
7C1009B-25
7C1009B-35
20
25
75
70
10
10
2
-
San Jose
•
CA 95134
•
408-943-2600
Revised August 24, 2001
) and Write
1
) input
2
) is then
7
0
1
32
OE
31
A
10
30
CE
29
I/O
7
28
I/O
6
27
I/O
5
26
I/O
4
25
I/O
3
24
GND
23
I/O
2
22
I/O
1
21
I/O
0
20
A
0
19
A
1
18
A
2
17
A
3
109B–3
35
60
10
-