CY7C1350B-143AC Cypress Semiconductor Corp, CY7C1350B-143AC Datasheet

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CY7C1350B-143AC

Manufacturer Part Number
CY7C1350B-143AC
Description
IC SRAM 4.5MBIT 143MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1350B-143AC

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4.5M (128K x 36)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1100
Cypress Semiconductor Corporation
Document #: 38-05045 Rev. *A
Features
Selection Guide
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Logic Block Diagram
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
• Pin compatible and functionally equivalent to ZBT™
• Supports 166-MHz bus operations with zero wait states
• Internally self-timed output buffer control to eliminate
• Fully registered (inputs and outputs) for pipelined
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power (17.325 mW max.)
devices IDT71V546, MT55L128L36P, and MCM63Z736
the need to use OE
operation
— Data is transferred on every clock
— 3.5 ns (for 166-MHz device)
— 3.8 ns (for 150-MHz device)
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
ADV/LD
BWS
MODE
A
128Kx36 Pipelined SRAM with NoBL™ Architecture
OE
CLK
CEN
[16:0]
WE
CE 1
CE 2
CE
[3:0]
3
17
and WRITE
CONTROL
LOGIC
Commercial
Commercial
3901 North First Street
PRELIMINARY
17
-166
400
3.5
Functional Description
The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350B is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on ev-
ery clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1350B is pin/func-
tionally
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
5
CE
128Kx36
MEMORY
ARRAY
Data-In REG.
[3:0]
Q
D
) and a Write Enable (WE) input. All writes are con-
-150
compatible
36
375
3.8
San Jose
5
36
-143
350
4.0
36
5
to
CA 95134
ZBT
36
-133
300
4.2
5
Revised January 18, 2003
DQ
SRAMs
DP
CY7C1350B
1
[31:0]
, CE
[3:0]
-100
250
5.0
5
2
, CE
408-943-2600
IDT71V546,
3
) and an
200
-80
7.0
5

Related parts for CY7C1350B-143AC

CY7C1350B-143AC Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-05045 Rev. *A PRELIMINARY Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consec- utive Read/Write operations with data being transferred on ev- ery clock cycle ...

Page 2

... Pin Configuration DDQ DDQ DDQ DDQ DDQ Document #: 38-05045 Rev. *A PRELIMINARY 100-Pin TQFP CY7C1350B CY7C1350B DDQ DDQ DDQ DDQ Page ...

Page 3

... When left floating MODE will default HIGH inter- leaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. CY7C1350B Description controls DQ and DP 0 ...

Page 4

... Do Not Use pins. These pins should be left floating or tied to V Burst Read Accesses The CY7C1350B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above ...

Page 5

... OE. Burst Write Accesses The CY7C1350B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ad- dress, as described in the Single Write Access section above ...

Page 6

... Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range 55°C to +125°C 0.5V to +4.6V Range Com’l 0. 0.5V DDQ 0. 0.5V Ind’l DDQ . Bytes written are determined by BWS x [3:0] CY7C1350B BWS BWS ...

Page 7

... MHz > V – 0. DDQ 6.6-ns cycle, 150 MHz 1/t MAX CYC 7.0-ns cycle, 143 MHz 7.5-ns cycle, 133 MHz 10.0-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz CY7C1350B Min. Max. Unit 3.135 3.465 V 3.135 3.465 V 2.4 V 0.4 V 2 ...

Page 8

... AC Test Loads. Document #: 38-05045 Rev. *A PRELIMINARY Test Conditions T = 25° MHz 3.3V 3.3V DDQ [13] R=317 3.3V OUTPUT 5 pF R=351 INCLUDING JIG AND SCOPE 1350B-2 (b) Test Conditions CY7C1350B Max [14] ALL INPUT PULSES 3.0V GND Symbol TQFP Typ. Units 28 C C/W JC Unit Notes 12 12 ...

Page 9

... SRAMs when sharing the same EOLZ CHZ CLZ CY7C1350B -143 -133 -100 7.5 10 12.5 3.0 4.0 4.0 3.0 4.0 4.0 2.0 2.2 2.5 0.5 ...

Page 10

... DS CHZ Out Out define a write cycle (see Write Cycle Description table). [3: and CE . All chip enables need to be active in order to select UNDEFINED = DON’T CARE CY7C1350B t t CENH CENS CEN HIGH blocks all synchronous inputs RA6 RA7 DOH Out In Out t CHZ Q7 Out ...

Page 11

... PRELIMINARY t CYC WA2 CHZ Q1+2 Q1+3 Q1+1 Out Out Out define a write cycle (see Write Cycle Description table). [3: and CE . All chip enables need to be active in order to select UNDEFINED = DON’T CARE CY7C1350B RA3 t CLZ D2+2 D2+3 D2 input signals. [3:0] Page Out ...

Page 12

... Switching Waveforms (continued) OE Timing Ordering Information Speed (MHz) Ordering Code 166 CY7C1350B-166AC 150 CY7C1350B-150AC 143 CY7C1350B-143AC 133 CY7C1350B-133AC CY7C1350B-133AI 100 CY7C1350B-100AC CY7C1350B-100AI Shaded areas contain advanced information. Document #: 38-05045 Rev. *A PRELIMINARY OE t EOHZ Three-state I/O’s t EOLZ Package Name Package Type A101 100-Lead ( ...

Page 13

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1350B 51-85050-A Page ...

Page 14

... Document Title: CY7C1350B 128K x 36 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05045 Issue REV. ECN NO. Date ** 109953 01/07/02 *A 123109 01/18/03 Document #: 38-05045 Rev. *A PRELIMINARY Orig. of Change SZV Change from Spec number: 38-00910 to 38-05045 RBI Add power up requirements to AC test loads and waveforms information ...

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