CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet

no-image

CY7C1354A-166BGC

Manufacturer Part Number
CY7C1354A-166BGC
Description
IC SRAM 9MBIT 166MHZ 119BGA
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1354A-166BGC

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
119-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1108

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1354A-166BGC
Manufacturer:
CYPRESS
Quantity:
40
Features
Functional Description
The
GVT71512ZC18 SRAMs are designed to eliminate dead cy-
cles when transitioning from READ to WRITE or vice versa.
These SRAMs are optimized for 100 percent bus utilization
and achieve Zero Bus Latency (ZBL)/No Bus Latency (NoBL).
They integrate 262,144x36 and 524,288x18 SRAM cells, re-
spectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. These employ
high-speed, low-power CMOS designs using advanced triple-
layer polysilicon, double-layer metal technology. Each memory
cell consists of four transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Selection Guide
Cypress Semiconductor Corporation
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA) Com’l
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
• Zero Bus Latency, no dead cycles between write and
• Fast clock speed: 200, 166, 133, and 100 MHz
• Fast access time: 3.2, 3.6, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate
• Single 3.3V –5% and +5% power supply V
• Separate V
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and con-
• Interleaved or linear 4-word burst capability
• Individual byte write (BWa–BWd) control (may be tied
• CKE pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Snooze Mode for low power standby
• JTAG boundary scan
• Low profile 119-bump, 14-mm x 22-mm BGA (Ball Grid
read cycles
the need to control OE
trol signal registers for fully pipelined applications
LOW)
Array) and 100-pin TQFP packages
256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture
CY7C1354A/GVT71256ZC36
CCQ
for 3.3V or 2.5V I/O
and
Com’l
3901 North First Street
CC
CY7C1356A/
PRELIMINARY
7C1354A-200
71256ZC36-5
7C1356A-200
71512ZC18-5
560
3.2
30
Chip Enables (CE, CE
Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc,
and BWd), and Read-Write Control (R/W). BWc and BWd ap-
ply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data oc-
curs, either read or write.
A clock enable (CKE) pin allows operation of the
CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CKE) is HIGH and the internal device reg-
isters will hold their previous values.
There are three chip enable pins (CE, CE
user to deselect the device when desired. If any one of these
three are not active when ADV/LD is LOW, no new memory
operation can be initiated and any burst cycle in progress is
stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high-impedance
state two cycles after chip is deselected or a write cycle is
initiated.
The
GVT71512ZC18 have an on-chip 2-bit burst counter. In the
burst
CY7C1356A/GVT71512ZC18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD=LOW) or increment the internal burst counter
(ADV/LD=HIGH)
Output Enable (OE), Snooze Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to LOW
if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
CY7C1354A/GVT71256ZC36
7C1354A-166
7C1356A-166
71256ZC36-6
71512ZC18-6
mode,
San Jose
480
3.6
30
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
the
2
and CE
CY7C1354A/GVT71256ZC36
71256ZC36-7.5
71512ZC18-7.5
7C1354A-133
7C1356A-133
CA 95134
2
410
), Cycle Start Input (ADV/LD),
4.2
30
2
and
, CE
71256ZC36-10
71512ZC18-10
7C1354A-100
7C1356A-100
2
) that allow the
408-943-2600
May 18, 2000
CY7C1356A/
350
5.0
30
and

Related parts for CY7C1354A-166BGC

CY7C1354A-166BGC Summary of contents

Page 1

... Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc, and BWd), and Read-Write Control (R/W). BWc and BWd ap- ply to CY7C1354A/GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data oc- curs, either read or write ...

Page 2

... The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. PRELIMINARY [1] Address Control Input Registers Control Logic Output Registers Output Buffers [1] Address Control Input Registers Control Logic Output Registers Output Buffers 2 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Sel Mux DQa-DQd Sel Mux DQa, DQb ...

Page 3

... DQb DQa 18 63 DQa DQb CCQ 61 CCQ DQa DQb 22 59 DQa DQb 23 58 DQa DPb 24 57 DQa CCQ 54 CCQ DQa DQa DQa CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 CY7C1356A GVT71512ZC18 65 (512K x 18 CCQ DQa DQa DQa CCQ DQa DQa DQa DQa V CCQ V SS DQa DQa ...

Page 4

... Pin Configurations (continued) CY7C1354A/GVT71256ZC36 (256K x 36 BGA CCQ DQc E DQc F V CCQ G DQc H DQc J V CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CY7C1356A/GVT71512ZC18 (512K x 18 BGA CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb CCQ PRELIMINARY 119-Ball Bump BGA ...

Page 5

... CLK Input- Clock: This is the clock input to CY7C1354A/GVT71256ZC36. Synchronous Except for OE, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK. ...

Page 6

... R/W is sampled HIGH. The appropriate byte(s) of data are written into the device two cycles later. BWa con- trols DQa pins; BWb controls DQb pins. BWx can all be tied LOW if always doing write to the entire 18-bit word. 6 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description . GND ...

Page 7

... Output IEEE 1149.1 test output. LVTTL-level output. If Serial Bound- ary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect). V Supply Power Supply: +3.3V –5% and +5 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description are used 2 sampled LOW, along with ADV/ used with CE 2 has inverted polarity but oth- 2 ...

Page 8

... Linear Burst Address Table (MODE = V Fourth First Address Address [5] (internal) (external) A...A A... A...A A... A...A A... A...A A... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description or to GND. CC [4] BWb BWc BWd Second Third Fourth Address Address Address (internal) (internal) (internal) A...A A...A A... A...A A...A A... ...

Page 9

... Previous Address Cycle Used R/W ADV/ Deselect External H L Read Next External H L Read Next External L L Write Next External L L Write Next being HIGH. CE equals L means CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 n+24 n+25 n+26 n+ CKE BWx OE (2 cycles later High High High High-Z ...

Page 10

... The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number. 10 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ) ...

Page 11

... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. 11 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 plus The ...

Page 12

... IDLE Note: 21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. PRELIMINARY 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram 12 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [21 ...

Page 13

... OLC [23, 25 100 A OHC [23 8.0 mA OLT [23 8.0 mA OHT (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Selection Circuitry [22] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –30 30 –5.0 5 ...

Page 14

... THMX t Capture Hold CH Notes: 26. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register 27. Test conditions are specified using the load in TAP AC test conditions. PRELIMINARY [26, 27] Over the Operating Range Description 14 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Min. Max ...

Page 15

... TAP Timing and Test Conditions 1.5V 50 TDO GND ( TEST CLOCK (TCK) TEST MODE SELECT (TMS) TEST DATA IN (TDI) TEST DATA OUT (TDO) PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ALL INPUT PULSES 3.0V 1.5V 1 ...

Page 16

... Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Places the bypass register between TDI and TDO. This instruction does not affect device operations. 16 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description Reserved for revision number. Defines depth of 256K or 512K words. ...

Page 17

... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump ID CE2 92 6B BWa 93 5L BWb 94 5G BWc 95 3G BWd 96 3L CE2 100 2A DQc 1 2D DQc 2 1E DQc 3 2F DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 2E DQc 12 2G DQc DQd 18 2K DQd 19 1L DQd 22 2M ...

Page 18

... R/W 88 PRELIMINARY Boundary Scan Order (512K x 18) Bit# Bump CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump ID CLK 89 4K CE2 92 6B BWa 93 5L BWb 94 3G CE2 100 2A DQb 8 1D DQb 9 2E DQb 12 2G DQb DQb 18 2K DQb 19 1L DQb 22 2M DQb 23 1N DQb ...

Page 19

... Device deselected; all inputs < > all inputs static Max.; CLK frequency = 0 CC Device deselected; all inputs < > MAX CLK cycle time > t Min means no input lines are changing. CYC 19 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Ambient [11] Temperature +70 C 3.3V Min. Max. 2.0 V +0.3 CC 2.0 4.6 –0.5 0 ...

Page 20

... AC Test Loads and Waveforms for 2.5V I 1.25V t (a) PRELIMINARY Description Test Conditions MHz 3.3V CC Test Conditions 317 3. 351 (b) 2. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Typ. Max. Unit 6.5 pF Symbol TQFP Typ. Units 25 C C/W JC ALL INPUT PULSES 90% 90% 10% 10% 1.0 ns (c) ALL INPUT PULSES 90% 90% 10% 10% 1 ...

Page 21

... KQHZ KQLZ OEHZ 21 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 -7.5/ -10/ 133 MHz 100 MHz Max. Min. Max. Min. Max. 7.5 10 2.6 3.5 2.6 3.5 3.6 4.2 5.0 1.0 1 ...

Page 22

... BURST PIPELINE READ Pipeline Read . Q(A ) represents the first output from the external address etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined 2 is HIGH CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 (Burst Wraps around to initial state) Q(A +2) Q(A +3) Q ...

Page 23

... Burst Pipeline Write Pipeline Write ) represents the first input to the external address etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the 2 23 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 BW (Burst Wraps around to initial state) D(A +2) D(A ...

Page 24

... KQ DATA Out (Q) Read DATA In (D) Note: 46. Q(A ) represents the first output from the external address A 1 PRELIMINARY BW KQHZ KQLZ KQX Q Read D Write Write . D(A ) represents the input data to the SRAM corresponding to address CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Q(A ) Q(A 6 Read D ...

Page 25

... CKE when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM will retain their previous state. PRELIMINARY KQHZ Q KQLZ KQX 25 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ...

Page 26

... This allows for any pending data transfers (reads or writes completed. PRELIMINARY KQHZ Q KQX D(A ) represents the input data to the SRAM corresponding to address sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 OEHZ Q D etc. 3 ...

Page 27

... Ordering Information Speed (MHz) Ordering Code 200 CY7C1354A-200AC/ GVT71256ZC36-5 CY7C1354A-200BGC/ GVT71256ZC36B-5 166 CY7C1354A-166AC/ GVT71256ZC36-6 CY7C1354A-166BGC/ GVT71256ZC36B-6 133 CY7C1354A-133AC/ GVT71256ZC36-7.5 CY7C1354A-133BGC/ GVT71256ZC36B-7.5 100 CY7C1354A-100AC/ GVT71256ZC36-10 CY7C1354A-100BGC/ GVT71256ZC36B-10 200 CY7C1356A-200AC/ GVT71512ZC18-5 CY7C1356A-200BGC/ GVT71512ZC18B-5 166 CY7C1356A-166AC/ GVT71512ZC18-6 CY7C1356A-166BGC/ GVT71512ZC18B-6 133 CY7C1356A-133AC/ GVT71512ZC18-7.5 CY7C1356A-133BGC/ GVT71512ZC18B-7.5 ...

Page 28

... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 PRELIMINARY 28 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 51-85050-A ...

Page 29

... Package Diagrams (continued) Revision History Document Title: CY7C1354A/CY7C1356A Document Number: 38-00992 REV. ECN NO. ISSUE DATE ** 3000 4/21/00 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Related keywords