PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet
PSD4235G2V-12UI
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PSD4235G2V-12UI Summary of contents
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... Features ■ Dual bank Flash memories – 4 Mbit of Primary Flash memory (8 uniform sectors, 32K x 16) – 256 Kbit Secondary Flash memory with 4 sectors – Concurrent operation: read from one memory while erasing and writing the other ■ 64 Kbit SRAM ■ PLD with macrocells – ...
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... Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Data-In registers - port 6.2 Data-out registers - port 6.3 Direction registers - ports 6.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/129 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 12 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 13 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSD4235G2 ...
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... Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2 Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.4 Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5 Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.6 Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.7 Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.8 Toggle flag (DQ6) - DQ14 for Motorola ...
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... Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.3 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3 Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13 Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2 Memory Select configuration for MCUs with separate Program and Data spaces ...
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PSD4235G2 18.3 Loading and Reading the output macrocells (OMC 18.4 The OMC Mask register . . . . . . . . . ...
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... Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 99 23 Programming in-circuit using the JTAG serial interface . . . . . . . . . . 101 23.1 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 23.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 23.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 102 24 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6/129 PSD4235G2 ...
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PSD4235G2 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 24. PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25. VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26. Memory_ID0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 27. Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 28. Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 29. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 30. Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 31. Status bits for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 32. DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 33. Output macrocell Port and Data bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 34 ...
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PSD4235G2 Table 49. PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 50. APD counter ...
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... PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. PSDsoft Express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5. Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 6. Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 7. Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 8. 8031 memory modules - separate space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 9. 8031 memory modules - combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 10. Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 11. PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 12 ...
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PSD4235G2 Figure 49. LQFP80 - 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 124 List of figures ...
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... The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: 1.1.1 First time programming How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. 1.1.2 Inventory build-up of pre-programmed devices How do I maintain an accurate count of pre-programmed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer ...
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... A built-in page register breaks the MCU address limit. 1.2.3 Separate Program and Data space How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51XA will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. ...
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Summary description Figure 1. Logic diagram Table 1. Pin names PA0-PA7 PB0-PB7 PC0-PC7 PD0-PD3 PE0-PE7 PF0-PF7 PG0-PG7 AD0-AD15 CNTL0-CNTL2 RESET 14/129 CNTL0- CNTL2 PSD4xxxGx 16 AD0-AD15 RESET V SS Pin Port-A Port-B Port-C Port-D Port-E Port-F Port-G ...
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PSD4235G2 Table 1. Pin names (continued Figure 2. LQFP connections PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND AD5 10 AD6 11 AD7 12 AD8 ...
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Pin description 2 Pin description Table 2. Pin description (for the LQFP package) Pin name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules your MCU has ...
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... Active low input. Resets I/O Ports, PLD macrocells and some of the Configuration RESET 39 I registers and JTAG registers. Must be low at Power-up. Reset also aborts any Flash memory Program or Erase cycle that is currently in progress. These pins make up Port A. These port pins are configurable and can have the I/O following functions: CMOS 1 ...
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... Transparent PLD input (can also be PLD input for address A16 and above). PD2 PSD Chip Select input (CSI). When low, the MCU can access the PSD memory Open and I/O. When high, the PSD memory blocks are disabled to conserve power. The Drain falling edge of this signal can be used to get the device out of Power-down mode ...
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PSD4235G2 Table 2. Pin description (for the LQFP package) (continued) Pin name Pin Type I/O PE7 pin of Port E. This port pin can be configured to have the following functions: CMOS PE7 78 1. MCU I/O - standard output ...
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Pin description Figure 3. PSD block diagram 1. Additional address lines can be brought in to the device via Port 20/129 PSD4235G2 AI04990b ...
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... Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in The 4 Mbit primary Flash memory is the main memory of the PSD divided into 8 equally-sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable ...
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... The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. different functional blocks of the PSD. 3.8 Page register The 8-bit Page register expands the address range of the MCU 256 times. The paged address can be used as part of the address space to access external memory and 22/129 Table 4 Name Inputs 82 ...
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... PSD4235G2 peripherals, or internal memory and I/O. The Page register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP. 3.9 Power management unit (PMU) The power management unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements ...
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... The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels ...
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... Automatically configures MCU bus interface and other Define PSD Pin and Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Point and click definition of combin- atorial and registered logic in CPLD. Access HDL is available if needed ...
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... Read only - Primary Flash Sector C0 Protection Read only - PSD Security and C2 Secondary Flash memory Sector Protection C7 Enables JTAG Port B0 Power Management register 0 B4 Power Management register 2 E0 Page register Places PSD memory areas in E2 Program and/or Data space on an individual basis. PSD4235G2 ...
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... Register name A B Memory_ID0 Memory_ID1 1. Other registers that are not part of the I/O ports. PSD register description and address offsets Port Port Port Port (1) Other Description Read only - SRAM and Primary F0 memory size Read only - Secondary memory type F1 and size 27/129 ...
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Register bit definition 6 Register bit definition All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. 6.1 Data-In registers - port ...
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PSD4235G2 6.5 Drive registers - Ports Table 11. Drive registers - Ports Bit 7 Bit 6 Port pin 7 Port pin 6 Port pin <i>: 0: Port pin <i> is ...
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... Read-only register Table 19. Flash Memory Protection register Bit 7 Bit 6 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Sec<i>_Prot: 1: Primary Flash memory Sector <i> is write protected. 0: Primary Flash memory Sector <i> is not write protected. 30/129 Bit 5 Bit 4 Bit 3 Mcella 5 Mcella 4 Mcella 3 Bit 5 ...
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... Bit 6 Security_ not used Bit Sec<i>_Prot: 1: Secondary Flash memory Sector <i> is write protected. 0: Secondary Flash memory Sector <i> is not write protected. Security_Bit: 0: Security bit in device has not been set. 1: Security bit in device has been set. 6.13 JTAG Enable register Table 21. ...
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Register bit definition APD Enable: 0: Automatic Power-down (APD) is disabled. 1: Automatic Power-down (APD) is enabled. PLD Turbo: 0: PLD Turbo is on. 1: PLD Turbo is off, saving power. PLD Array CLK: 0: CLKIN to the PLD AND ...
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... Boot_data cannot access Secondary NVM in 80C51XA modes can access Secondary NVM in 80C51XA modes. FL_data cannot access Primary Flash memory in 80C51XA modes can access Primary Flash memory in 80C51XA modes. Peripheral mode 0 = Peripheral mode of Port F is disabled Peripheral mode of Port F is enabled. Bit 5 ...
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... Primary Flash memory size is 256 Kbit 2h: Primary Flash memory size is 512 Kbit 3h = Primary Flash memory size is 1 Mbit 4h = Primary Flash memory size is 2 Mbit 5h = Primary Flash memory size is 4 Mbit 6h = Primary Flash memory size is 8 Mbit S_size[3: There is no SRAM 1h = SRAM size is 16 Kbit ...
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... Primary Flash memory ● Secondary Flash memory ● SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft Express. Table 28 summarizes the sizes and organisations of the memory blocks. Table 28. Memory block size and organization ...
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... ROM device. However, Flash memory can only be erased and programmed using specific instructions. For example, the MCU cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a word into Flash memory, the MCU must execute a Program instruction, then test the status of the Programming event. This status test is achieved by a READ operation or polling Ready/Busy (PE4) ...
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... All bus cycles are WRITE bus cycles, except the ones with the “Read” label 2. All values are in hexadecimal Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed ...
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... The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. ...
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... The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of its Sector Select signals (FS0-FS7) is high, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is high ...
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... The Flash memory Sector Protection Status is read with an instruction composed of four operations: three specific WRITE operations and a READ operation (see READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory, or secondary Flash memory) can be read by the MCU accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space ...
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... CSBOOT3 is true, the Toggle Flag bit (DQ6/DQ14) bit toggles from 0 to ’1’ and 1 to ’0’ on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the value from the addressed memory location. The device is now accessible for a DQ5 DQ4 ...
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... Error flag (DQ5) - DQ13 for Motorola During a normal Program or Erase cycle, the Error Flag bit (DQ5/DQ13) is reset to '0.' This bit is set to ’1’ when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag bit (DQ5/DQ13) indicates the attempt to program a Flash memory bit, or bits, from the programmed state the erased state, 1, which is not a valid operation ...
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... Erase cycle is in progress or has completed. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the word to be programmed in Flash memory to check the status. The Data Polling bit (DQ7/DQ15) becomes the complement of the corresponding bit of the original data word to be programmed ...
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... When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location to be programmed in Flash memory to check the status. The Toggle Flag bit (DQ6/DQ14) toggles each time the MCU reads this location until the embedded algorithm is complete ...
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... To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode. Figure 6) ...
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... Programming Flash memory Figure 6. Data toggle flowchart 46/129 START READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address DQ6 No (DQ14) = Toggle Yes DQ5 No (DQ13 Yes READ DQ6 (DQ14) DQ6 No (DQ14) = Toggle Yes Program Program or Erase or Erase Cycle failed Cycle is complete ...
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... Before and during Erase timeout, any instruction other than Suspend Sector Erase and Resume Sector Erase, abort the cycle that is currently in progress, and reset the device to READ mode not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing. ...
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... The Toggle Flag bit (DQ6/DQ14) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag bit (DQ6/DQ14) stops toggling between 0.1µs and 15 µs after the Suspend Sector Erase instruction has been executed ...
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... A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes μs to return to the READ mode recommended that the Reset (RESET) pulse (except for Power-on Reset, as described in 25μ ...
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... SRAM 12 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express. 50/129 PSD4235G2 ...
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... The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the secondary Flash memory and primary Flash memory ...
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... The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are set to ’1’ (see Figure ...
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... PSD4235G2 13.5 80C51XA memory map example See the Application notes for examples. Figure 8. 8031 memory modules - separate space DPLD RS0 CSBOOT0-3 FS0-FS7 PSEN RD Figure 9. 8031 memory modules - combined space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 ...
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... DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed not all eight page register bits are needed for memory paging, these bits may be used in the CPLD for general logic. See Application Note AN1154 ...
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... PSD4235G2 15 Memory ID registers The 8-bit Read-only Memory Status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as shown in Table 27. Memory ID registers ...
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... PLDs are briefly discussed in the next few paragraphs, and in more detail in the following sections. Figure 11 The DPLD performs address decoding for internal components, such as memory, registers, and I/O ports Select signals. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic ...
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... PSD4235G2 Table 32. DPLD and CPLD inputs (continued) Input source Page register Macrocell A feedback Macrocell B feedback Flash memory Program Status bit 1. The address inputs are A19-A4 in 80C51XA mode. Input name PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy PLDS Number of signals 57/129 ...
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PLDS Figure 11. PLD diagram 58/129 PORTS I/O BUS INPUT PLD PSD4235G2 ...
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... Decode PLD (DPLD) The DPLD, shown in components. The DPLD can be used to generate the following decode signals: ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) ● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) ● ...
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Decode PLD (DPLD) Figure 12. DPLD logic array 1. The address inputs are A19-A4 when in 80C51XA mode 2. Additional address lines can be brought ino the PSD via Port 60/129 PSD4235G2 ...
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PSD4235G2 18 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight ...
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Complex PLD (CPLD) Figure 13. Macrocell and I/O port PRODUCT TERMS FROM OTHER MACROCELLS CPLD MACROCELLS PRODUCT TERM ALLOCATOR PRODUCT TERMS POLARITY SELECT PT CLOCK GLOBAL CLOCK CLOCK SELECT PT CLEAR PT OUTPUT ENABLE ( OE ) ...
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PSD4235G2 Table 33. Output macrocell Port and Data bit Assignments Output Macrocell Assignment McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7 18.2 Product Term Allocator The CPLD has a Product Term Allocator. ...
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... Complex PLD (CPLD) 18.3 Loading and Reading the output macrocells (OMC) The output macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see macrocells (OMC) can be loaded from the data bus by a MCU. Loading the output macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU ...
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PSD4235G2 Figure 14. CPLD output macrocell MASK REG. MACROCELL ALLOCATOR POLARITY PT CLK CLKIN FEEDBACK ( .FB ) 18.6 Input macrocells (IMC) The CPLD has 24 input macrocells (IMC), one for each pin ...
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Complex PLD (CPLD) Input macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. shows a typical configuration where the Master MCU writes to the Port A Data Out ...
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PSD4235G2 18.7 External Chip Select The CPLD also provides eight External Chip Select (ECS0-ECS7) outputs that can be used to select external devices. Each External Chip Select (ECS0-ECS7) consists of one product term that can be configured active high or ...
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Complex PLD (CPLD) Figure 17. Handshaking communication using input macrocells 68/129 PSD4235G2 ...
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PSD4235G2 19 MCU bus interface The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 16-bit MCUs, with their bus types and control signals, are shown in Table Table 34. ...
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MCU bus interface 19.1 PSD interface to a multiplexed bus Figure 18 shows an example of a system using a MCU with a 16-bit multiplexed bus and a PSD4235G2. The ADIO port on the PSD is connected directly to the ...
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PSD4235G2 19.2 PSD interface to a non-multiplexed 8-bit bus Figure 19 shows an example of a system using a MCU with a 16-bit non-multiplexed bus and a PSD4235G2. The address bus is connected to the ADIO Port, and the data ...
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MCU bus interface 19.4 MCU bus interface examples Figure 20 to Figure 25 and some popular MCUs. The PSD4235G2 Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified ...
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PSD4235G2 19.5 80C196 and 80C186 In Figure 20, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a PSD4235G2. The Read Strobe (RD, CNTL1), and Write Strobe (WR/WRL, CNTL0) signals are connected to the ...
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MCU bus interface 19.6 MC683xx and MC68HC16 Figure 21 shows a MC68331 with a 16-bit non-multiplexed data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The SIZ0 ...
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... CNTL2 pins. The 80C51XA improves bus throughput and performance by issuing burst cycles to fetch codes from memory. In burst cycles, address A19-A4 are latched internally by the PSD, while the 80C51XA drives the A3-A1 signals to fetch sequentially bytes of code. The PSD access time is then measured from address A3-A1 valid to data in valid. The PSD bus timing requirement in a burst cycle is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) is not required ...
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MCU bus interface 19.8 H8/300 Figure 23 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F (D0-D7) and Port G (D8-D15). The WRH signal is ...
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PSD4235G2 19.9 MMC2001 The Motorola MCORE MMC2001 MCU has a MOD input pin that selects interal or external boot ROM. The PSD can be configured as the external flash boot ROM or as extension to the internal ROM. The MMC2001 ...
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MCU bus interface Figure 24. Interfacing the PSD with an MMC2001 VCC_BAR Infineon C167CR 138 XTAL1 U3 CRYSTAL 137 XTAL2 65 P3.0/T0IN 66 P3.1/T6OUT 67 P3.2/CAPIN 68 P3.3/T3OUT 69 P3.4/T3EUD 70 P3.5/T4IN 73 P3.6/T3IN 74 P3.7/T2IN 75 P3.8/MRST 76 P3.9/MTSR ...
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PSD4235G2 Figure 25. Interfacing the PSD with a C167CR Vcc 144136129109 VccVccVccVccVccVccVccVccVccVcc 138 XTAL1 C167CR 137 XTAL2 65 P3.0/T0IN 66 P3.1/T6OUT 67 P3.2/CAPIN 68 P3.3/T3OUT 69 P3.4/T3UED 70 P3.5/T4IN 73 P3.6/T3IN 74 P3.7/T2IN 75 ...
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I/O ports 20 I/O ports There are seven programmable I/O ports: Ports and G. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express ...
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PSD4235G2 20.2 Port operating modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft Express, some by the MCU writing to the registers in CSIOP space, and some by both. The modes that can ...
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... MCUs. Note: Do not drive address signals with Address Out Mode to an external memory device intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set. ...
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PSD4235G2 Table 39. Port operating modes (continued) Port Mode Port A Address In Yes Data Port No Peripheral I/O Yes JTAG ISP No (2) MCU Reset mode No 1. Can be multiplexed with other I/O functions. 2. Available to Motorola ...
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... For MCUs that have more than 16 address signals, the higher addresses can be connected to Port and are routed as inputs to the PLDs. The address input can be latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the primary Flash memory, secondary Flash memory or SRAM is considered address input. 20.7 ...
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PSD4235G2 Figure 27. Peripheral I/O mode RD PSEL0 PSEL1 VM REGISTER BIT 7 WR 20.9 JTAG in-system programming (ISP) Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can multiplex JTAG operations with other functions ...
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I/O ports 20.11 Port Configuration registers (PCR) Each Port has a set of Port Configuration registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given ...
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PSD4235G2 (The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when ...
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I/O ports 20.14 Port Data registers The Port Data registers, shown in data from the ports. and MCU access for each register type. The registers are described next. 20.15 Data In Port pins are connected directly to the Data In ...
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PSD4235G2 Table 47. Port Data registers Register Name Mask macrocell Input macrocell Enable Out 20.20 Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A '1' indicates ...
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... Address Strobe (ALE/AS, PD0) ● CLKIN (PD1) as input to the macrocells Flip-flops and APD counter ● PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory, SRAM and CSIOP. ● Write Enable high-byte (WRH, PD3) input DBE input from a MC68HC912. ...
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PSD4235G2 Figure 29. Port D structure DATA OUT Register D WR READ MUX DIR Register D WR 20.23 Port E - functionality and structure Port E can be configured to perform one or more of the following functions (see ● ...
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I/O ports 20.24 Port F - functionality and structure Port F can be configured to perform one or more of the following functions: ● MCU I/O Mode ● CPLD output - External Chip Select (ECS7-ECS0) can be connected to Port ...
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PSD4235G2 Figure 30. Port E, F and G structure DATA OUT Register ADDRESS D Q ALE G Ext. CS (Port F) READ MUX CONTROL Register DIR Register ENABLE ...
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... PLDs. This is a good alternative to using the APD Unit, especially if your MCU has a chip select output. There is a slight penalty in memory access time when PSD Chip Select input (CSI, PD2) makes its initial transition from deselected to selected. ...
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... The PSD also returns to normal operation if either PSD Chip Select input (CSI, PD2) is low or the Reset (RESET) input is high. ● The MCU address/data bus is blocked from all memory and PLDs. ● Various signals can be blocked (prior to Power-down mode) from entering the PLDs by setting the appropriate bits in the Power Management Mode registers (PMMR) ...
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... Figure 31. APD unit APD EN PMMR0 BIT 1=1 ALE RESET CSI CLKIN DISABLE Primary and Secondary FLASH Memory and SRAM Table 49. PSD timing and standby current during Power-down mode PLD propagation Mode Power- Normal t down 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit ...
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... PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When low, the signal selects and enables the internal primary Flash memory, secondary Flash memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input (CSI, PD2) disables the primary Flash memory, secondary Flash memory, and SRAM, and reduces the PSD power consumption ...
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Power management 21.7 Input control signals The PSD provides the option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and Write Enable high-byte (WRH/DBE, PD3)) to the PLD to save ...
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... During this period, the device loads internal configurations, clears CC some of the registers and sets the Flash memory into Operating mode. After the rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period, t (maximum 120 ns), before the first memory access is allowed. ...
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Power-on Reset, Warm Reset and Power-down Table 51. Status During Power-On Reset, Warm Reset and Power-down mode (continued) Port configuration Cleared to ’0’ by internal Macrocells Flip-flop status Power-On Reset Initialized, based on the selection in PSDsoft (1) VM register ...
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... The JTAG Serial Interface on the PSD can be enabled on Port E (see blocks (primary Flash memory and secondary Flash memory), PLD logic, and PSD Configuration bits may be programmed through the JTAG-ISC Serial Interface. A blank device can be mounted on a printed circuit board and programmed using JTAG In-System Programming (ISP) ...
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... TSTAT is high when the PSD4235G2 device is in READ mode (primary Flash memory and secondary Flash memory contents can be read). TSTAT is low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory . TSTAT and TERR can be configured as open-drain type signals with a JTAG command. ...
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PSD4235G2 Table 52. JTAG port signals (continued) Port E pin PE4 PE5 Programming in-circuit using the JTAG serial interface JTAG signals TSTAT Status TERR Error Flag Description 103/129 ...
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... Initial delivery state When delivered from ST, the PSD device has all bits in the memory and PLDs set to '1.' The PSD Configuration register bits are set to '0.' The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 53. ...
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... Before calculating the total power consumption, determine the percentage of time that the PSD is in each mode. Also, the supply power is considerably different if the Turbo bit is 0. ● The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Terms (PT) used. ● ...
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... SRAM access % I/O access % Normal % Power-down mode (from fitter report total product terms Turbo Mode I total CC 1. This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based mA. OUT Conditions Highest Composite PLD input frequency = 8 MHz = 4 MHz = 80 (no additional power above base) ...
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... I/O access % Normal % Power-down Mode (from fitter report total product terms Turbo Mode I total CC 1. This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on I mA. 108/129 Conditions Highest Composite PLD input frequency = 8 MHz = 4 MHz = 80 (no additional power above base) ...
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PSD4235G2 Table 56. Operating conditions Symbol V Supply voltage CC Ambient operating temperature (industrial Ambient operating temperature (commercial) Table 57. AC signal letters for PLD timings Letter A Address input C CEout output D Input data E E ...
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DC and AC parameters Table 59. AC measurement conditions Symbol C Load Capacitance L 1. Output Hi-Z is defined as the point where data out is no longer driven. (1) Table 60. Capacitance Symbol Parameter C Input capacitance (for input ...
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PSD4235G2 Figure 37. Switching waveforms - key WAVEFORMS Table 61. DC characteristics Symbol Parameter V input high voltage voltage IH V input low voltage IL RESET high level input V IH1 voltage V RESET low level input voltage IL1 V ...
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... CC Supply 5 (Note ) Current Flash memory SRAM PLD AC Adder Flash memory AC Adder I (AC) CC SRAM AC Adder 1. Reset (RESET) has hysteresis CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. Please see Figure 34 for the PLD current calculation. ...
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PSD4235G2 Table 62. CPLD Combinatorial timing (continued) Symbol Parameter CPLD register Clear or t ARPW Preset Pulse Width t CPLD Array Delay ARD 1. Fast Slew Rate output available on Port C and Port F. Table 63. CPLD macrocell Synchronous ...
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DC and AC parameters Table 64. CPLD macrocell Asynchronous clock mode timing Symbol Parameter Conditions Maximum frequency 1/(t External Feedback Maximum frequency f MAXA Internal 1/(t SA Feedback (f ) CNTA Maximum frequency 1/(t Pipelined Data t Input setup time ...
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PSD4235G2 Figure 40. Asynchronous RESET / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 41. Asynchronous clock mode timing (product term clock) CLOCK INPUT REGISTERED OUTPUT Figure 42. Input macrocell timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 65. Input ...
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DC and AC parameters Table 66. Program, WRITE and Erase times Symbol Flash Program (1) Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / ...
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PSD4235G2 Figure 44. READ timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV 1. t and t are not required for 80C251 in Page Mode or ...
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DC and AC parameters Table 67. READ timing (continued) Symbol Parameter t R/W Hold time After Enable ELTL Address input Valid to t AVPV Address output Delay 1. Any input used to select an internal PSD function timing ...
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PSD4235G2 Figure 45. WRITE timing ALE MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS Table 68. WRITE timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address setup ...
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... WR has the same timing as E, DS, LDS, UDS, WRL, and WRH signals. 3. tWHAX when writing to the output macrocell registers AB and BC. 4. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. 5. Assuming WRITE is active before data becomes valid. ...
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PSD4235G2 Table 69. Port F Peripheral Data Mode Read timing Symbol Parameter t Address Valid to Data Valid AVQV–PF t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode t Data ...
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... Warm Reset NLNH–A t RESET high to Operational Device OPR 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode. Table 72. Power-down timing Symbol Parameter t ALE Access time from Power-down ...
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PSD4235G2 Table 73. ISC timing Symbol Parameter Clock (TCK, PC1) frequency (except for t ISCCF PLD) Clock (TCK, PC1) high time (except for t ISCCH PLD) Clock (TCK, PC1) low time (except for t ISCCL PLD) t Clock (TCK, PC1) ...
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Package mechanical 27 Package mechanical In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ® ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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PSD4235G2 Table 74. LQFP80 - 80-lead plastic thin, quad, flat package mechanical data Symb ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. mm Typ Min Max 0.600 0.450 0.750 1.000 ...
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... Option T = Tape & Reel Packing 1. The 3.3V±10% devices are not covered by this data sheet, but by the PSD4235G2V data sheet. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...
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PSD4235G2 Appendix A Pin assignments Table 76. PSD4235G2 LQFP80 Pin Pin No. Pin No. Pin assignments Pin No. assignments 1 PD2 21 2 PD3 22 3 AD0 23 4 AD1 24 5 AD2 25 6 AD3 26 7 AD4 27 ...
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Revision history 29 Revision history Table 77. Document revision history Date May 01, 2001 01-Aug-01 12-Sep-01 14-Dec-01 11-Mar-04 12-Feb-09 128/129 Revision 1.0 Initial release as a WSI document 1.1 Timing parameters updated 2.0 Document rewritten using the ST template Information ...
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... PSD4235G2 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...