CY62256L-70PXC

Manufacturer Part NumberCY62256L-70PXC
DescriptionIC SRAM 256KBIT 70NS 28DIP
ManufacturerCypress Semiconductor Corp
CY62256L-70PXC datasheets

Availability: In stock

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of CY62256L-70PXC

Format - MemoryRAMMemory TypeSRAM
Memory Size256K (32K x 8)Speed70ns
InterfaceParallelVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°CPackage / Case28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names428-1782
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
Page 1/11

Download datasheet (452Kb)Embed
Next
Features
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE
features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
HIGH chip enable (CE
), and active LOW output enable (OE)
2
and three-state drivers. Both devices have an automatic
Logic Block Diagram
INPUT BUFFER
A
1
A
2
A
3
A
256 x 32 x 8
4
ARRA Y
A
5
A
6
A
7
A
8
CE
1
COLUMN DECODER
CE
2
WE
OE
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. **
power-down feature (CE
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
, CE
, and OE
1
2
inputs are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
through A
0
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
), an active
1
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
DOWN
3901 North First Street
8K x 8 Static RAM
), reducing the power consumption
1
is HIGH, data on the eight data
2
through I/O
) is written into the memory
0
7
). Reading the device is accomplished by
12
active HIGH, while WE remains inactive or
2
Pin Configuration
SOIC
Top View
NC
V
1
28
A
WE
2
27
4
A
CE
3
26
5
A
A
6
4
25
0
A
A
7
5
24
A
A
8
6
23
1
A
OE
9
7
22
A
A
10
8
21
A
CE
11
9
20
2
A
I/O
12
10
19
I/O
I/O
0
11
18
I/O
I/O
3
1
12
17
I/O
I/O
2
13
16
GND
I/O
14
15
4
5
6
7
,
San Jose
CA 95134
408-943-2600
Revised June 27, 2005
CY6264
and WE
1
and OE
1
CC
2
3
2
1
0
1
7
6
5
4
3

CY62256L-70PXC Summary of contents

  • Page 1

    ... COLUMN DECODER Cypress Semiconductor Corporation Document #: 001-02367 Rev. ** power-down feature (CE by over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When and inputs are both LOW and CE input/output pins (I/O ...

  • Page 2

    Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Shaded areas contain advance information. Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature ...

  • Page 3

    ... At any given temperature and voltage condition The internal write time of the memory is defined by the overlap of CE signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

  • Page 4

    AC Test Loads and Waveforms R1 481Ω 5V OUTPUT OUTPUT 255Ω INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT Switching Waveforms [8, 9] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [10, ...

  • Page 5

    Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) ADDRESS DATA IN DATA I/O DATA UNDEFINED Write Cycle No. 2 (CE Controlled) ADDRESS DATA IN DATA I/O ...

  • Page 6

    Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 1.0 0.8 0.6 0.4 0 0.0 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.1 ...

  • Page 7

    Truth Table Address Designators Address Name A10 A11 A12 Document ...

  • Page 8

    Ordering Information Speed (ns) Ordering Code 55 CY6264-55SC 70 CY6264-70SC 55 CY6264-55SNC 55 CY6264-55SNXC 70 CY6264-70SNC 70 CY6264-70SNXC 70 CY6264-70SNI 70 CY6264-70SNXI Shaded areas contain advance information. Package Diagrams 28-lead (300 mil) SNC Package Outline (Narrow Body) SN28 0.702 0.710 ...

  • Page 9

    ... Document #: 001-02367 Rev. ** © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

  • Page 10

    Document History Page Document Title:CY6264 Static RAM Document Number: 001-02367 REV. ECN NO. Issue Date ** 384870 See ECN Document #: 001-02367 Rev. ** Orig. of Change Description of Change PCI Spec # change from 38-00425 to ...

  • Page 11

    ...