Features
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE
features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
HIGH chip enable (CE
), and active LOW output enable (OE)
2
and three-state drivers. Both devices have an automatic
Logic Block Diagram
INPUT BUFFER
A
1
A
2
A
3
A
256 x 32 x 8
4
ARRA Y
A
5
A
6
A
7
A
8
CE
1
COLUMN DECODER
CE
2
WE
OE
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. **
power-down feature (CE
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
, CE
, and OE
1
2
inputs are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
through A
0
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
), an active
1
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
DOWN
•
3901 North First Street
8K x 8 Static RAM
), reducing the power consumption
1
is HIGH, data on the eight data
2
through I/O
) is written into the memory
0
7
). Reading the device is accomplished by
12
active HIGH, while WE remains inactive or
2
Pin Configuration
SOIC
Top View
NC
V
1
28
A
WE
2
27
4
A
CE
3
26
5
A
A
6
4
25
0
A
A
7
5
24
A
A
8
6
23
1
A
OE
9
7
22
A
A
10
8
21
A
CE
11
9
20
2
A
I/O
12
10
19
I/O
I/O
0
11
18
I/O
I/O
3
1
12
17
I/O
I/O
2
13
16
GND
I/O
14
15
4
5
6
7
,
•
San Jose
CA 95134
•
408-943-2600
Revised June 27, 2005
CY6264
and WE
1
and OE
1
CC
2
3
2
1
0
1
7
6
5
4
3