CY7C09369V-6AXC Cypress Semiconductor Corp, CY7C09369V-6AXC Datasheet
CY7C09369V-6AXC
Specifications of CY7C09369V-6AXC
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CY7C09369V-6AXC Summary of contents
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... Upper and lower byte controls for bus matching ■ Automatic power down ■ Commercial and industrial temperature ranges ■ Pb-Free 100-pin TQFP package available [ (max) I/O I/O Control Control True Dual-Ported RAM Array • 198 Champion Court • San Jose CY7C09269V/79V/89V CY7C09369V/79V/89V 0 ...
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... Figure 1. 100-Pin TQFP (Top View CY7C09289V (64K x 16) CY7C09279V (32K x 16) CY7C09269V (16K x 16 pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible CC CY7C09269V/79V/89V CY7C09369V/79V/89V A9R 74 A10R 73 A11R 72 A12R 71 A13R [6] 70 A14R [7] 69 A15R LBR 65 UBR ...
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... Typical Standby Current for I (mA) SB1 (Both Ports TTL Level) Typical Standby Current for I (μA) SB3 (Both Ports CMOS Level) Notes 9. This pin is NC for CY7C09369V. 10. This pin is NC for CY7C09369V and CY7C09379V. Document #: 38-06056 Rev. *C Figure 2. 100-Pin TQFP (Top View ...
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... NC No Connect. V Power Input. CC Functional Description The CY7C09269V/79V/89V and CY7C09369V/79V/89V are high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any [11] location in memory . Registers on control, address, and data lines allow for minimal setup and hold times ...
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... Indust. 125 170 Test Conditions T = 25° MHz 3. and CE must be asserted to their active states ( CY7C09269V/79V/89V CY7C09369V/79V/89V +0.5V CC Ambient Temperature V CC 3.3V ± 300 mV 0°C to +70°C 3.3V ± 300 mV –40°C to +85°C Unit -9 -12 Typ Max Min Typ Max 2 ...
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... TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) 3.0V GND Capacitance (pF) (b) Load Derating Curve CY7C09269V/79V/89V CY7C09369V/79V/89V 3. 590Ω OUTPUT 435Ω (c) Three-State Delay(Load 2) (Used for and t CKLZ OLZ including scope and jig) [14] ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ ...
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... Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Setup Time CCS Notes 15. Test conditions used are Load 2. 16. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06056 Rev. *C CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V [ Min Max Min Max Min Max ...
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... Q n n+1 t OHZ t CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09269V/79V/89V CY7C09369V/79V/89V [17, 18, 19, 20 n+3 t CKHZ Q n OLZ t OE [17, 18, 19, 20 ...
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... CD2 HC CD2 SC CKHZ CKLZ NO MATCH t CD1 NO MATCH t CWDD VALID . for the Left Port, which is being written to. IH CY7C09269V/79V/89V CY7C09369V/79V/89V CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ [23, 24, 25, 26] t CD1 VALID >maximum specified, then data is not valid until CWDD CCS Page [+] Feedback ...
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... During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity. Document #: 38-06056 Rev n+1 n CD2 CKHZ Q n READ NO OPERATION n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09269V/79V/89V CY7C09369V/79V/89V [20, 27, 28, 29 n+3 n CD2 CKLZ Q n+3 WRITE READ [20, 27, 28, 29 n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback [+] Feedback ...
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... DATA OUT OE Document #: 38-06056 Rev n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION n+1 n+2 n n+2 n OHZ READ WRITE CY7C09269V/79V/89V CY7C09369V/79V/89V [18, 20, 28, 29 n+3 n CD1 CD1 Q n CKLZ DC WRITE READ [18, 20, 27, 28, 29 n+4 n CD1 t CD1 Q n CKLZ DC READ Page [+] Feedback [+] Feedback ...
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... IH Document #: 38-06056 Rev SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER n+1 n+2 READ WITH COUNTER . CY7C09269V/79V/89V CY7C09369V/79V/89V [30] t HAD t HCN Q Q n+2 n+3 READ WITH COUNTER [30 SAD HAD t t SCN HCN Q n+3 READ COUNTER HOLD WITH COUNTER Page [+] Feedback ...
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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06056 Rev n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09269V/79V/89V CY7C09369V/79V/89V [31, 32 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page [+] Feedback [+] Feedback ...
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... OUT COUNTER RESET Notes 33 UB, and 34. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06056 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09269V/79V/89V CY7C09369V/79V/89V [20, 27, 33 READ READ ADDRESS n Page [+] Feedback [+] Feedback ...
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... out( out( out(n+ out(n+ CY7C09269V/79V/89V CY7C09369V/79V/89V Operation 17 [38] Deselected [38] Deselected Write [35] Read Outputs Disabled Mode Operation Reset Counter Reset to Address 0 Load Address Load into Counter Hold External Address Blocked—Counter Disabled Increment Counter Enabled—Internal Address Generation Increment Counter Enabled—Internal Address ...
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... Thin Quad Flat Pack (Pb-Free) 51-85048 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack (Pb-Free) 51-85048 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack (Pb-Free) CY7C09269V/79V/89V CY7C09369V/79V/89V Operating Range Commercial Commercial Commercial Industrial Commercial Operating Range ...
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... Ordering Information (Continued) 16K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09369V-6AC CY7C09369V-6AXC [2] 7.5 CY7C09369V-7AC CY7C09369V-7AXC CY7C09369V-7AI 9 CY7C09369V-9AC CY7C09369V-9AXC CY7C09369V-9AI 12 CY7C09369V-12AC CY7C09369V-12AXC 32K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09379V-6AC CY7C09379V-6AXC [2] 7.5 CY7C09379V-7AC 9 CY7C09379V-9AC ...
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... Package Diagrams Figure 17. 100-Pin Thin Plastic Quad Flat Pack (TQFP), 51-85048 Document #: 38-06056 Rev. *C CY7C09269V/79V/89V CY7C09369V/79V/89V 51-85048 *C Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM Document Number: 38-06056 Revision ECN Submission Date ** 110215 12/18/01 *A 122306 12/27/02 *B 344354 See ECN *C 2678221 03/25/2009 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...