CY7C1426AV18-167BZXC Cypress Semiconductor Corp, CY7C1426AV18-167BZXC Datasheet
CY7C1426AV18-167BZXC
Specifications of CY7C1426AV18-167BZXC
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CY7C1426AV18-167BZXC Summary of contents
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... Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1411AV18) or 9-bit words (CY7C1426AV18) or 18-bit words (CY7C1413AV18) or 36-bit words (CY7C1415AV18) that burst sequentially into or out of the device. Since data can be transferred into and out ...
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... Logic Block Diagram (CY7C1411AV18) D [7:0] 8 Address Register A (19: CLK K Gen. DOFF V REF WPS Control Logic NWS [1:0] Logic Block Diagram (CY7C1426AV18) D [8:0] 9 Address Register A (19: CLK K Gen. DOFF V REF WPS Control Logic BWS [0] Document Number: 38-05614 Rev. *C Write Write Write Write ...
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... Reg Reg Register Control Logic Read Data Reg Reg. Reg. 36 Reg. Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg. 144 72 Reg. Reg. 72 Reg. CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 A (18:0) 19 RPS [17: (17:0) 18 RPS [35:0] 36 Page [+] Feedback ...
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... DDQ TDO TCK A Document Number: 38-05614 Rev. *C CY7C1411AV18 ( NC/144M NC/144M WPS NWS NC/288M K NWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1426AV18 ( WPS NC K NC/144M A NC/288M K BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 RPS DDQ V NC ...
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... K WPS BWS BWS BWS BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 NC/72M CQ RPS DDQ DDQ DDQ DDQ DDQ REF DDQ DDQ DDQ TMS TDI NC/144M CQ RPS A D17 Q17 Q8 V D16 D15 D7 Q16 SS V Q15 D6 Q6 DDQ ...
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... These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized arrays each for CY7C1411AV18 arrays each for CY7C1426AV18, arrays each of 512K x 18) for CY7C1413AV18 and arrays each of 256K x 36) for CY7C1415AV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1411AV18 and CY7C1426AV18, 19 address inputs for CY7C1413AV18 and 18 address inputs for CY7C1415AV18 ...
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... Each access consists of four 8-bit data transfers in the case of CY7C1411AV18, four 9-bit data transfers in the case of CY7C1426AV18, four 18-bit data transfers in the case of CY7C1413AV18, and four 36-bit data in the case of CY7C1415AV18 transfers in two clock cycles. Accesses for both ports are initiated on the Positive Input Clock (K) ...
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... QDR-II. In the single clock mode generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 to allow the SRAM to adjust its SS ...
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... 50ohms Vt = Vddq D( ↑ D K(t +1) ↑ ↑ ↑ Q( ↑ ↑ ↑ ↑ High High-Z Previous State Previous State ↑ represents rising edge. CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 SRAM # 250ohms CQ/CQ High High-Z Previous State ...
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... CY7C1413AV18 − only the upper byte (D [17:9] unaltered. No data is written into the devices during this portion of a write operation. , NWS , BWS 0 1 CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 ) is written into the device. D will remain [3:0] [7: written into the device. D will remain [17: written into the device ...
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... D will remain unaltered. [26:0] – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Comments CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 ) are written [35:0] ) are written [35: written [8:0] ...
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... TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Page [+] Feedback ...
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... The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. Document Number: 38-05614 Rev. *C CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...
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... Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 38-05614 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... Over the Operating Range Test Conditions = −2 −100 µ 2 100 µ GND ≤ V ≤ [13, 14] Over the Operating Range Description / ns CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Selection TDO Circuitry Min. Max. Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD µ ...
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... TCYC t TMSS t TMSH t TDIS t TDIH t TDOV Value CY7C1426AV18 CY7C1413AV18 000 000 00000110100 00000110100 1 1 CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Min. Max. Unit ALL INPUT PULSES 0.9V t TDOX CY7C1415AV18 Description 000 Version number. type of SRAM. 00000110100 Allows unique identification of SRAM vendor. 1 Indicates the presence register ...
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... Do Not Use: This instruction is reserved for future use. 110 Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Description Page [+] Feedback ...
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... Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...
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... If the input clock is unstable and the DLL is enabled, then the DLL may lock to an incorrect frequency, causing unstable SRAM behavior REF > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tied to V DDQ ) CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 . Start Normal Operation Page [+] Feedback ...
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... RQ <= 350Ωs. − /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Ambient [21] [21 DDQ 1.8 ± 0.1V 1. Min. Typ. Max. Unit 1 ...
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... V = 0.75V REF V 0.75V R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω (b) /I and load capacitance shown in ( Test Loads CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 Max. Unit 165 FBGA Package Unit 17.2 °C/W 3.2 °C/W [24] ALL INPUT PULSES 1.25V 0.75V Slew Rate = 2 V/ ...
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... This part has a voltage regulator internally; t POWER can be initiated. 27. For D2 data signal on CY7C1426AV18 device are specified with a load capacitance part ( Test Loads. Transition is measured ± 100 mV from steady-state voltage. 28 ...
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... CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 200 MHz 167 MHz Unit 0.45 – 0.45 – 0.50 ns – –0.45 – –0.50 – ns 0.30 – 0.35 – ...
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... WRITE READ WRITE KHKH D13 D10 D11 D12 Q00 Q01 Q02 CLZ t DOH t KHKH t CCQO t CQOH t CCQO t CQOH DON’T CARE CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 NOP D30 D31 D32 D33 Q03 Q20 Q21 Q22 Q23 t CHZ t CQDOH t CQD UNDEFINED Page [+] Feedback ...
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... Ordering Code Diagram 167 CY7C1411AV18-167BZC 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1426AV18-167BZC CY7C1413AV18-167BZC CY7C1415AV18-167BZC CY7C1411AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1426AV18-167BZXC CY7C1413AV18-167BZXC CY7C1415AV18-167BZXC CY7C1411AV18-167BZI 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1426AV18-167BZI CY7C1413AV18-167BZI CY7C1415AV18-167BZI CY7C1411AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array ( ...
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... CY7C1413AV18-278BZXI CY7C1415AV18-278BZXI 300 CY7C1411AV18-300BZC 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1426AV18-300BZC CY7C1413AV18-300BZC CY7C1415AV18-300BZC CY7C1411AV18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1426AV18-300BZXC CY7C1413AV18-300BZXC CY7C1415AV18-300BZXC CY7C1411AV18-300BZI 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1426AV18-300BZI CY7C1413AV18-300BZI CY7C1415AV18-300BZI CY7C1411AV18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array ( ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 ...
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... Document History Page Document Title: CY7C1411AV18/CY7C1426AV18/CY7C1413AV18/CY7C1415AV18 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 38-05614 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE DESCRIPTION OF CHANGE ** 247331 See ECN *A 326519 See ECN *B 413953 See ECN *C 468029 See ECN Document Number: 38-05614 Rev. *C SYT ...