M29DW128F70NF6E NUMONYX, M29DW128F70NF6E Datasheet - Page 18

• Manufacturer Part Number: M29DW128F70NF6E
• Description: IC FLASH 128MBIT 70NS 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29DW128F70NF6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bus operations
3
3.1
3.2
3.3
3.4
18/94
Bus operations
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Dual operations are possible in the M29DW128F, thanks to its multiple bank architecture.
While programming or erasing in one banks, read operations are possible in any of the other
banks. Write operations are only allowed in one bank at a time.
See
on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by
the memory and do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words
and is addressed by the address inputs A0-A2.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, V
High, V
waveforms,
for details of when the output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See
and
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see
the memory will continue to use the Program/Erase Supply Current, I
Erase operations until the operation completes.
Table 27
Table 3
IH
. The Data Inputs/Outputs will output the value, see
Figure 13: Page Read AC
and
and
Table
Table
6, Bus Operations, for a summary. Typically glitches of less than 5ns
28, Write AC Characteristics, for details of the timing requirements.
IL
Table 25: DC
, to Chip Enable and Output Enable and keeping Write Enable
IH
CC2
, the memory enters Standby mode and the Data
, Chip Enable should be held within V
waveforms, and
Characteristics. During program or erase operations
Figure 14
and
Table 26: Read AC
Figure
Figure 12: Random Read AC
15, Write AC Waveforms,
CC3
CC
, for Program or
± 0.2V. For the
characteristics,
M29DW128F
IH
IH
,
.