M29DW128F70ZA6F NUMONYX, M29DW128F70ZA6F Datasheet

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... Byte/Word typical – 4 Words / 8 Bytes Program – 32-Word Write Buffer Erase Verify Memory blocks – Quadruple Bank Memory Array: 16Mbit+48Mbit+48Mbit+16Mbit – Parameter Blocks (at Top and Bottom) Dual Operation – While Program or Erase in one bank, Read in any of the other banks Program/Erase Suspend and Resume modes – ...

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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M29DW128F 4.2 Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 7 Status Register . . . . . . . . . . . . . . . . . . ...

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... M29DW128F Appendix A Block addresses and Read/Modify Protection Groups . . . . . . . . . 69 Appendix B Common Flash Interface (CFI Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 C.1 Factory Locked Section of the Extended Block . . . . . . . . . . . . . . . . . . . . . 83 C.2 Customer Lockable Section of the Extended Block Appendix D High Voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 D.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Appendix E Flowcharts ...

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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M29DW128F List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Summary description 1 Summary description The M29DW128F is a 128 Mbit (16Mb x8 or 8Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. At Power-up the memory defaults to its Read mode. The M29DW128F features an asymmetrical block architecture, with 16 parameter and 254 main blocks, divided into four Banks and D, providing multiple Bank operations ...

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M29DW128F Table 1. Signal names A0-A22 DQ0-DQ7 DQ8-DQ14 DQ15A– BYTE / The x8 organization is only available in TSOP56 Package while the x16 organization is available for ...

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Summary description Table 2. Bank architecture Bank Bank size A 16 Mbit B 48 Mbit C 48 Mbit D 16 Mbit Figure 2. TSOP connections V PP /WP 10/94 Parameter Blocks No. of Block size Blocks 8 8 Kbytes/ 4 ...

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M29DW128F Figure 3. TBGA connections (top view through package ...

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Summary description Figure 4. Block Addresses (x8) 000000h 8 KBytes 001FFFh 00E000h 8 KBytes 00FFFFh Bank A 010000h 64 KBytes 01FFFFh 1F0000h 64 KBytes 1FFFFFh 200000h 64 KBytes 20FFFFh Bank B 7F0000h 64 KBytes 7FFFFFh 1. Also see Appendix A ...

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M29DW128F Figure 5. Block Addresses (x16) 000000h 4 KWords 000FFFh 007000h 4 KWords 007FFFh Bank A 008000h 32 KWords 00FFFFh 0F8000h 32 KWords 0FFFFFh 100000h 32 KWord 107FFFh Bank B 3F8000h 32 KWords 3FFFFFh 1. Also see Appendix A, Table ...

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... Figure 1: Logic connected to this device. 2.1 Address Inputs (A0-A22) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. 2.2 Data Inputs/Outputs (DQ0-DQ7) The Data I/O outputs the data stored at the selected address during a Bus Read operation ...

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... M29DW128F 2.7 Write Enable (W) The Write Enable pin, W, controls the Bus Write operation of the memory’s Command Interface. 2.8 V Write Protect (V PP/ The V /Write Protect pin provides two functions. The V PP use an external high voltage power supply to reduce the time required for Program operations ...

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... A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/Word Organization Select (BYTE used to switch between the x8 and x16 Bus modes of the memory when the M29DW128F is delivered in TSOP56 package. When Byte/Word Organization Select is Low the memory mode, when it is High, V ...

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... This prevents Bus Write operations from accidentally damaging the data LKO during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the V Ground pin to decouple the current surges from the power supply ...

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... Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 8 Words and is addressed by the address inputs A0-A2 ...

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... They require V 3.6.1 Read Electronic Signature The memory has two codes, the Manufacturer code and the Device code used to identify the memory. These codes can accessed by performing read operations with control signals and addresses set as shown in issuing an Auto Select command (see 3 ...

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Bus operations 3.6.5 Temporary Unprotect of high voltage Protected Blocks The RP pin can be used to temporarily unprotect all the blocks previously protected using the In-System or the Programmer protection technique (High Voltage techniques). Refer to Temporary Unprotect (RP). ...

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M29DW128F Table 6. Bus operations, 16-bit mode Operation E G Bus Read Bus Write Output Disable Standby ...

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Hardware Protection 4 Hardware Protection The M29DW128F features hardware protection/unprotection. Refer to block protection/unprotection using V 4.1 Write Protect The V /WP pin protects the four outermost parameter blocks (refer detailed description of the signals). 4.2 Temporary ...

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M29DW128F 5 Software Protection The M29DW128F has two different Software Protection modes: the Standard Protection mode and the Password Protection mode. On first use all parts default to the Standard Protection mode and the customer is free to activate the ...

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... The Lock-Down bit is set by issuing the Set Lock-Down bit Command not cleared using a command, but through a hardware reset or a power-down/power-up sequence. The parts are shipped with the Non-Volatile Modify Protection bits set to ‘0’. Locked blocks and Non-Volatile Locked blocks can co-exist in the same memory array. Refer to Table 10: Block Protection status details on the block protection mechanism ...

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... If the Password provided is not correct, the Lock-Down bit remains locked and the state of the Non- Volatile Modify Protection bits cannot be modified. The Password is a 64-bit code located in the memory space. It must be programmed by the user prior to selecting the Password Protection mode. The Password is programmed by issuing a Password Program command and checked by issuing a Password Verify command ...

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Software Protection Figure 6. Block Protection State diagram Set Standard Protection Standard Protection Figure 7. Software Protection scheme Parameter Block Main Blocks Block Lock/Unlock Protection Non-Volatile Protection 26/94 Default: Standard Protection Mode Non-Volatile Modify Lock Bit ...

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... The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to Read mode. If the Read/Reset command is issued during the time-out of a Block erase operation, the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. ...

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... Once in Read CFI Query mode Bus Read operations to the same bank will output data from the Common Flash Interface (CFI) Memory Area. If the read operations are to a different bank from the one specified in the command then the read operations will output the contents of the memory array and not the CFI data ...

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... When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Command interface ...

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... Table 18 for value) of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued ...

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M29DW128F It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will ...

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... Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final Write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. ...

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M29DW128F Table 11. Standard Commands, 8-bit mode Command Read/Reset Manufacturer Code Device Code Auto Extended Block Protection Select Indicator Block Protection Status Program Blank Verify Command Verify Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 1. Grey ...

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Command interface Table 12. Standard Commands, 16-bit mode Command Read/Reset Manufacturer Code Device Code Auto Select Extended Block Protection Indicator Block Protection Status Program Blank Verify Command Verify Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 1. ...

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... Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. ...

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... Write to Buffer and Program operation not possible to detect Program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. ...

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M29DW128F 6.2.2 Write to Buffer and Program Confirm command The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and Program command and to program the N+1 Words/bytes loaded in the Write Buffer by ...

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... When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The Unlock Bypass Program command can then be issued to program addresses within the bank, or the Unlock Bypass Reset command can be issued to return the bank to Read mode. In Unlock Bypass mode the memory can be read Read mode. 38/94 ...

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... Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. ...

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Command interface Table 14. Fast Program Commands, 16-bit mode Command Write to Buffer and Program Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program ...

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... Unlock Bypass mode is not available. The Extended Block cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode only array cell locations (Bank A) with the same addresses as the Extended Block are not accessible. In Extended Block mode dual operations are allowed and the Extended Block physically belongs to Bank A ...

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Command interface 6.3.3 Set Extended Block Protection bit command The Set Extended Block Protection bit command programs the Extended Block Protection bit to ‘1’ thus preventing the second section of the Extended Block from being programmed. A Read/Reset command must ...

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M29DW128F 6.3.6 Password Verify command The Password Verify Command is used to verify the Password used in Password Protection mode. To verify the 64-bit Password, the complete command sequence must be entered four times at four consecutive addresses selected by ...

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Command interface 6.3.10 Set Standard Protection mode command The Set Standard Protection Mode command puts the device in Standard Protection mode by programming the Standard Protection Mode Lock bit to ‘1’. Six cycles are required to issue the Standard Protection ...

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M29DW128F 6.3.14 Clear Non-Volatile Modify Protection bits command This command is used to clear all Non-Volatile Modify Protection bits. No specific block address is required. If the Lock-Down bit is set to ‘1’, the command will fail. Six cycles are ...

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Command interface Table 15. Block Protection Commands, 8-bit mode Command Set Extended Block Protection bit Verify Extended Block Protection bit Enter Extended Block Exit Extended Block 1. OW Extended Block Protection bit Address (A7-A0=’00011010’), X Don’t Care. All values in ...

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M29DW128F Table 16. Block Protection Commands, 16-bit mode (continued) Command 1st Add Data Add Data Add Data Verify Non- Volatile Modify 4 555 AA 2AA Protection bit Clear Non- Volatile Modify 6 555 AA 2AA Protection (12)(13)(14) bits Set Lock-Down ...

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Command interface Table 17. Protection Command Addresses Bit Password Protection Mode Lock bit Address (PL) Standard Protection Mode Lock bit Address (SL) Non-Volatile Modify Protection bit Address (NVMP) Extended Block Protection bit Address (OW) Table 18. Program, Erase Times and ...

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... DQ7, not its complement. During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling bit will change from a ’ ...

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... Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’ ...

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M29DW128F Table 19. Status Register bits Operation Address Program Bank Address Program During Erase Bank Address Suspend Write to Buffer and Bank Address Program Abort Program Error Bank Address Chip Erase Any Address Erasing Block Block Erase before timeout Non-Erasing ...

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Status Register Figure 9. Toggle flowchart Address of Bank being Programmed or Erased. 52/94 START READ DQ6 ADDRESS = BA READ DQ5 & DQ6 ADDRESS = BA DQ6 NO = TOGGLE YES NO DQ5 = 1 YES ...

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... The Multiple Bank Architecture of the M29DW128F gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased ...

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Dual Operations and Multiple Bank architecture Table 21. Dual Operations allowed in same Bank Status of Bank Read/ Reset Idle Yes Programming No Erasing No Program (6) Yes Suspended (6) Erase Suspended Yes 1. Read Status Register is not a ...

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M29DW128F 9 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ...

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DC and AC parameters 10 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests ...

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M29DW128F Table 24. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 25. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (1) I Supply ...

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DC and AC parameters Figure 12. Random Read AC waveforms A0-A22/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH 58/94 tAVAV VALID tAVQV tELQV tELQX tGLQX tGLQV tBHQV tBLQZ M29DW128F tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID AI08970 ...

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M29DW128F Figure 13. Page Read AC waveforms DC and AC parameters 59/94 ...

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DC and AC parameters Table 26. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC t t Address Valid to Output Valid (Page) AVQV1 PAGE ...

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M29DW128F Figure 14. Write AC waveforms, Write Enable Controlled A0-A22/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 27. Write AC characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC ...

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DC and AC parameters Figure 15. Write AC waveforms, Chip Enable Controlled A0-A22/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 28. Write AC characteristics, Chip Enable Controlled Symbol Alt t t Address Valid to Next Address ...

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M29DW128F Figure 16. Toggle and Alternative Toggle bits mechanism, Chip Enable Controlled Address Outside the Bank A0-A22 being Programmed or Erased E G Data (1) (2) DQ2 /DQ6 Read Operation outside the Bank Being Programmed or Erased 1. The Toggle ...

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DC and AC parameters Figure 18. Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing tPLPX Figure 19. Reset/Block Temporary Unprotect During Program/Erase Operation AC waveforms Figure 20. Accelerated Program Timing waveforms V ...

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M29DW128F Table 30. Reset/Block Temporary Unprotect AC characteristics Symbol Alt RP Low to Read mode, during Program or ( PLYH READY Erase Pulse Width PLPX High to Write Enable Low, Chip Enable ...

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Package mechanical 11 Package mechanical Figure 21. TSOP56 – 56 lead Plastic Thin Small Outline 20mm, package outline TSOP-b 1. Drawing is not to scale. Table 31. TSOP56 – 56 lead Plastic Thin Small Outline 20mm, ...

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M29DW128F Figure 22. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline BALL "A1" Drawing is not to scale. Table 32. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical ...

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... This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office ...

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M29DW128F Appendix A Block addresses and Read/Modify Protection Groups Table 34. Block Addresses and Protection Groups Size Bank Block (kbytes/KWords) 0 8/4 1 8/4 2 8/4 3 8/4 4 8/4 5 8/4 6 8/4 7 8/4 8 64/32 9 64/32 ...

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Block addresses and Read/Modify Protection Groups Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 27 64/32 28 64/32 29 64/32 30 64/32 31 64/32 32 64/32 33 64/32 34 64/32 35 64/32 36 64/32 37 64/32 ...

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M29DW128F Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 59 64/32 60 64/32 61 64/32 62 64/32 63 64/32 64 64/32 65 64/32 66 64/32 67 64/32 68 64/32 69 64/32 70 64/32 71 64/32 72 ...

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Block addresses and Read/Modify Protection Groups Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 91 64/32 92 64/32 93 64/32 94 64/32 95 64/32 96 64/32 97 64/32 98 64/32 99 64/32 100 64/32 101 64/32 ...

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M29DW128F Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 123 64/32 124 64/32 125 64/32 126 64/32 127 64/32 128 64/32 129 64/32 130 64/32 131 64/32 132 64/32 133 64/32 134 64/32 135 64/32 136 ...

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Block addresses and Read/Modify Protection Groups Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 155 64/32 156 64/32 157 64/32 158 64/32 159 64/32 160 64/32 161 64/32 162 64/32 163 64/32 164 64/32 165 64/32 ...

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M29DW128F Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 187 64/32 188 64/32 189 64/32 190 64/32 191 64/32 192 64/32 193 64/32 194 64/32 195 64/32 196 64/32 197 64/32 198 64/32 199 64/32 200 ...

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Block addresses and Read/Modify Protection Groups Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 219 64/32 220 64/32 221 64/32 222 64/32 223 64/32 224 64/32 225 64/32 226 64/32 227 64/32 228 64/32 229 64/32 ...

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M29DW128F Table 34. Block Addresses and Protection Groups (continued) Size Bank Block (kbytes/KWords) 251 64/32 252 64/32 253 64/32 254 64/32 255 64/32 256 64/32 257 64/32 258 64/32 259 64/32 260 64/32 261 64/32 262 8/4 263 8/4 264 ...

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... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...

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M29DW128F Table 37. CFI Query System Interface information Address Data x16 x8 1Bh 36h 0027h 1Ch 38h 0036h 1Dh 3Ah 00B5h 1Eh 3Ch 00C5h 1Fh 3Eh 0004h 20h 40h 0000h 21h 42h 0009h 22h 44h 0000h 23h 46h 0005h 24h ...

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Common Flash Interface (CFI) Table 38. Device Geometry Definition Address Data x16 x8 27h 4Eh 0018h Device Size = 2 TBGA64 0001h (x16 only) 28h 50h TSOP56 0002h (x8/x16) 29h 52h 0000h Packages 2Ah 54h 0006h Maximum number of bytes ...

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M29DW128F Table 39. Primary Algorithm-Specific Extended Query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h 44h 88h 0033h 45h 8Ah 000Ch 46h 8Ch 0002h 47h 8Eh 0001h 48h 90h 0001h 49h ...

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Common Flash Interface (CFI) Table 39. Primary Algorithm-Specific Extended Query table (continued) Address Data x16 x8 59h B2h 0060h 5Ah B4h 0060h 5Bh B6h 0027h 1. The values given in the above table are valid for both packages. Table 40. ...

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... Its status is indicated by bit DQ6 and DQ7. When DQ7 is set to ‘1’ and DQ6 to ‘0’, it indicates that this second memory area is Customer Lockable. When DQ7 and DQ6 are both set to ‘1’, it indicates that the second part of the Extended Block is Customer Locked and protected from program operations. Bit DQ7 being permanently locked to either ‘ ...

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... Extended Memory Block C.2 Customer Lockable Section of the Extended Block The device is delivered with the second section of the Extended Block "Customer Lockable": bits DQ7 and DQ6 are set to '1' and '0' respectively the customer to program and protect this section of the Extended Block but care must be taken because the protection is not reversible. ...

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... High Voltage Block Protection The High Voltage Block Protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. ...

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... The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP (1) . This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in flowchart ...

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M29DW128F Appendix E Flowcharts Figure 23. Programmer equipment Group Protect flowchart 1. Block Protection Groups are shown in START ADDRESS = GROUP ADDRESS ...

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Flowcharts Figure 24. Programmer equipment Chip Unprotect flowchart NO ++n = 1000 FAIL 1. Block Protection Groups are shown in 88/94 START PROTECT ALL GROUPS CURRENT GROUP = ...

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M29DW128F Figure 25. In-System equipment Group Protect flowchart 1. Block Protection Groups are shown can be either when using the In-System Technique to protect the Extended Block START n = ...

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Flowcharts Figure 26. In-System equipment Chip Unprotect flowchart NO ++n = 1000 YES ISSUE READ/RESET COMMAND FAIL 1. Block Protection Groups are shown in 90/94 START PROTECT ALL GROUPS CURRENT GROUP = 0 ...

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M29DW128F Figure 27. Write to Buffer and Program flowchart and Pseudo Code NO DQ1 = 1 YES 1. n+1 is the number of addresses to be programmed Write to Buffer and Program Abort and Reset must be issued ...

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Flowcharts 3. When the block address is specified, any address in the selected block address space is acceptable. However when loading Write Buffer address with data, all addresses must fall within the selected Write Buffer page. 4. DQ7 must be ...

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M29DW128F Revision history Table 43. Document revision history Date 02-Aug-2005 13-Oct-2005 02-Dec-2005 13-Mar-2006 13-Jun-2006 20-Jun-2006 26-Oct-2006 Revision 1.0 First Issue derived from the M29DW128F/FS datasheet revision 0.5. Table 18: Program, Erase Times and Program, Erase Endurance 2.0 Cycles updated. Datasheet ...

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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...