M29F800DB55N6 NUMONYX, M29F800DB55N6 Datasheet - Page 12

• Manufacturer Part Number: M29F800DB55N6
• Description: IC FLASH 8MBIT 55NS 48TSOP
• Manufacturer: NUMONYX

Specifications of M29F800DB55N6

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal descriptions
2
2.0.1
2.0.2
2.0.3
2.0.4
2.0.5
2.0.6
2.0.7
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Signal descriptions
See
connected to this device.
Address Inputs (A0-A18)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the Command
Interface of the internal state machine.
Data Inputs/Outputs (DQ8-DQ14)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, V
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, V
When BYTE is Low, V
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE is High
and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
Figure 1: Logic
diagram, and
IL
IH
, this pin behaves as an address pin; DQ15A–1 Low will select the
, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
IH
. When BYTE is Low, V
Table 1: Signal names
IH
, all other pins are ignored.
for a brief overview of the signals
IL
, these pins are not used and are
M29F800DT