M25P128-VME6TG NUMONYX, M25P128-VME6TG Datasheet
M25P128-VME6TG
Specifications of M25P128-VME6TG
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M25P128-VME6TG Summary of contents
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... JEDEC standard two-byte signature (2018h) More than 10,000 erase/program cycles per sector More than 20-year data retention RoHS compliant packages March 2010 128-Mbit, low-voltage, serial flash memory with 54-MHz SPI bus interface = 9 V) for Rev 6 M25P128 VDFPN8 (ME (MLP8) SO16 (MF) 300 mils width 1/47 www.numonyx.com 1 ...
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... Fast program/erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Write enable (WREN 6.2 Write disable (WRDI 6.3 Read identification (RDID 6.4 Read status register (RDSR ...
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WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Power-up timing and VWI threshold for 65 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9. Power-up timing and VWI threshold for 130 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10 ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 ...
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... Description The M25P128 is a 128-Mbit (16 Mbit × 8) serial flash memory, with advanced write protection mechanisms and accessed by a high speed SPI-compatible bus, which allows clock frequency operation MHz The memory can be programmed 1 to 256 Bytes at a time, using the page program instruction ...
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... PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1. Figure 3. SO connections Don’t use 2. See Package mechanical section for package dimensions, and how to identify pin-1. Description M25P128 HOLD W M25P128 HOLD ...
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Signal description 2.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial data input (D) This input ...
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... If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register ...
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... Hold (HOLD) signals should be driven, High or Low as appropriate These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high- impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (e ...
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Figure 5. SPI modes supported CPOL CPHA MSB Q MSB AI01438B 11/47 ...
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... Sector erase and bulk erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P128 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...
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... If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. 14/47 Memory content Protected area 0 none 1 ...
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Figure 6. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 15/47 ...
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... Memory organization The memory is organized as: 16777216 bytes (8 bits each) 64 sectors (2 Mbits, 262144 bytes each) 65536 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Table 3. Memory organization Sector Address Range FC0000h F80000h F40000h F00000h EC0000h E80000h E40000h E00000h DC0000h D80000h D40000h D00000h CC0000h C80000h C40000h C00000h BC0000h B80000h B40000h B00000h AC0000h A80000h A40000h A00000h 9C0000h 980000h 940000h 900000h 8C0000h 880000h 840000h 800000h 7C0000h 780000h 740000h ...
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... Table 3. Memory organization (continued) Sector 18/47 Address Range 700000h 6C0000h 680000h 640000h 600000h 5C0000h 580000h 540000h 500000h 4C0000h 480000h 440000h 400000h 3C0000h 380000h 340000h 300000h 2C0000h 280000h 240000h 200000h 1C0000h 180000h 140000h 100000h 0C0000h 080000h 040000h 000000h 73FFFFh 6FFFFFh 6BFFFFh 67FFFFh ...
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... That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected ...
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Write enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) ...
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... The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (18h) ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...
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Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read status register (RDSR) instruction sequence and data-out sequence Instruction D High Impedance Q ...
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... Status Register is Hardware write protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed sizes Memory Content (1) Protected Area Unprotected Area Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase Bulk Erase ...
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... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Page program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Figure 15. Page program (PP) instruction sequence Instruction Data Byte ...
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Sector erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Power-up and power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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... WI 1. These parameters are characterized only. 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Chip Selection Not Allowed tVSL ...
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Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 14. DC characteristics for 65 nm devices Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Operating Current (READ) CC3 I Operating Current (PP) CC4 Operating Current I CC5 (WRSR) I ...
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Table 15. AC characteristics for 65 nm devices Test conditions specified in Symbol Alt Data In Setup Time DVCH DSU t t Data In Hold Time CHDX Active Hold Time (relative to C) CHSH t ...
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When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. If only a single byte is programmed, the estimated ...
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Table 17. AC characteristics for 130 nm devices Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, WREN, WRDI RDID, RDSR, WRSR f Clock frequency for READ instructions R ...
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Table 17. AC characteristics for 130 nm devices (continued) Symbol Alt and t must be greater than or equal to 1 Value is guaranteed by characterization, not 100% tested in production. 3. Expressed ...
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Figure 21. Write protect setup and hold timing during WRSR when SRWD =1 W/V PP tWHSL High Impedance Q Figure 22. Hold timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439b tHHCH AI02032 ...
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Figure 23. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D Figure 24. V timing PPH PPH W/V PP tVPPHSL 42/47 tCH tCLQV tQLQH tQHQL End of PP (identified by WPI ...
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Package mechanical Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position ...
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Figure 26. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width B SO-H 1. Drawing is not to scale. Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width Symbol Typ A A1 ...
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... Numonyx sales office. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M25P128 – ...
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... Table 18: VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm, package mechanical V max modified in Table 10: Absolute maximum IO 3 Applied Numonyx branding. Removed references to multilevel cell technology and ECOPACK® packages. Added: Table 14: DC characteristics for 65 nm devices 4 AC characteristics for 65 nm ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...