M58BW016DB7T3TNX NUMONYX, M58BW016DB7T3TNX Datasheet
M58BW016DB7T3TNX
Specifications of M58BW016DB7T3TNX
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M58BW016DB7T3TNX Summary of contents
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... K write/erase cycling + 20 years data retention (minimum) ■ High reliability level with over 1 M write/erase cycling sustained ® ■ ECOPACK packages available March 2008 M58BW016DB M58BW016DT M58BW016FT M58BW016FB 16 Mbit (512 Kbit x 32, boot block, burst supply Flash memories LBGA80 10 × Rev 17 PQFP80 (T) LBGA 1/70 www.numonyx.com 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7 Program command ...
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Contents 5.6 Program suspend status (bit ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... A recovery time is required when the RP input goes High. The memory is offered in a PQFP80 ( mm) and LBGA80 (10 × 12 mm) package. The memories are supplied with all the bits erased (set to ’1’). ...
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Description Figure 1. Logic diagram 8/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DDQ V DDQIN V PP A0-A18 M58BW016DT M58BW016DB RP M58BW016FT M58BW016FB SSQ DQ0-DQ31 R AI11201b ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 1. Signal names Signal A0-A18 DQ0-DQ7 DQ8-DQ15 DQ16-DQ31 DDQ V DDQIN SSQ NC DU Description Address inputs ...
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Description Figure 2. PQFP connections (top view through package) DQ16 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 10/70 M58BW016DT, M58BW016DB, ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 3. LBGA connections (top view through package A15 B A16 C A17 D DQ3 E V DDQ F V SSQ G V DDQ H DQ13 I DQ15 J V DDQIN 1.1 Block protection ...
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Description Table 2. M58BW016DT and M58BW016FT top boot block addresses # ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 3. M58BW016DB and M58BW016FB bottom boot block addresses # ...
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... Address inputs (A0-A18) The address inputs are used to select the cells to access in the memory array during bus operations either to read or to program data. During bus write operations they control the commands sent to the command interface of the program/erase controller. Chip Enable must be Low when selecting the addresses ...
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... Latch Enable, L). 2.7 Reset/Power-down (RP) The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-down Low, V inhibited to protect data, the command interface and the program/erase controller are reset. The status register information is cleared and power consumption is reduced to deep power- down level ...
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... Valid Data Ready (R) The Valid Data Ready output open drain output that can be used, during synchronous burst read operations, to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready will be available ...
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... The input supply voltage GD A0-A18 and DQ0-DQ31, when used as inputs. 2.16 Program/erase supply voltage (V The program/erase supply voltage, V memory normally executes program and erase operations at V manufacturing environment, programming may be speeded up by applying a higher voltage level the V PPH The voltage level V cycles ...
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... Asynchronous latch controlled bus read Asynchronous latch controlled bus read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses ...
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... Asynchronous latch controlled bus write Asynchronous latch controlled bus write operations write to the command interface to send commands to the memory or to latch addresses and input data to program. Bus write operations are asynchronous, the clock don’t care during bus write operations. A valid asynchronous latch controlled bus write operation begins by setting the desired ...
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... Two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. The electronic signature is output by giving the Read Electronic Signature command. The manufacturer code is output when all the address inputs are at V ...
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... After an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of M9). The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. ...
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Bus operations Valid Data Ready may be configured (by bit M8 of burst configuration register valid immediately at the valid clock edge or one data cycle before the valid clock edge. Synchronous burst read will be suspended if ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.3 Burst configuration register The burst configuration register is used to configure the type of bus access that the memory will perform. The burst configuration register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into reset/power- down mode ...
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... Table 7: Burst configuration register the memory accepts; from a given starting address for each length. If either a continuous wrap burst read has been initiated the device will output data synchronously ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 7. Burst configuration register Bit M15 M14 M13-M11 M10 M9 M8 Valid data ready M7 M6 Valid clock edge M5-M4 M3 M2- latencies can be calculated as: (t number from ...
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Bus operations Table 8. Burst type definition Starting address sequential interleaved 0 0 0-1-2-3 0-1-2 1-2-3-0 1-0-3 2-3-0-1 2-3-0 3-0-1-2 3-2-1 – – 0 ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 4. Example burst configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 Figure 5. Example burst configuration X-2-2 ADD VALID L DQ 5-2-2-2 ...
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... Read Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area. One bus write cycle is required to issue the Read Query command. Once the command is issued subsequent bus read operations, depending on the address specified, read from the common Flash interface memory area. See ...
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... The Clear Status Register command can be used to reset bits and 5 in the status register to ‘0’. One bus write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to output the same data. ...
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... Program command The Program command is used to program the memory array. Two bus write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed in the program/erase controller and starts it ...
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... After the program/erase controller has paused, the memory will continue to output the status register until another command is issued. ...
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... The first cycle writes the setup command and the address corresponding to the set burst configuration register content. The second cycle writes the burst configuration register data and the confirm command. Once the command is issued the memory returns to read mode Read Memory Array command had been issued. ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 10. Program, erase times and program, erase endurance cycles Parameters Parameter Block (64 Kbits) Program Main Block (512 Kbits) Program Parameter Block Erase Main Block Erase Program Suspend Latency time Erase Suspend Latency time Program/Erase ...
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... When the erase suspend status bit is set to ‘0’, the program/erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the erase suspend status bit returns to ‘ ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 5.3 Erase status (bit 5) The erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The erase status bit should be read once the program/erase controller status bit is High (program/erase controller inactive). ...
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... When the program suspend status bit is set to ‘0’, the program/erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the program suspend status bit returns to ‘ ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 12. ...
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DC and AC parameters 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 7. AC measurement load circuit Table 14. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT ° MHz Sampled only, not 100% tested. 1.3 ...
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DC and AC parameters Table 15. DC characteristics Symbol Parameter I Input Leakage current LI I Output Leakage current LO I Supply current (Random Read) DD (1) I Supply current (Power-up) DDP-UP I Supply current (Burst Read) DDB Supply current ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 8. Asynchronous bus read AC waveforms A0-A18 DQ0-DQ31 . Table 16. Asynchronous bus read AC characteristics Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV ...
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DC and AC parameters Figure 9. Asynchronous latch controlled bus read AC waveforms A0-A18 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous latch controlled bus read AC characteristics Symbol t Address Valid to Latch Enable Low AVLL t Chip ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 10. Asynchronous page read AC waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous page read AC characteristics Symbol t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings see ...
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DC and AC parameters Figure 11. Asynchronous write AC waveforms 44/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 12. Asynchronous latch controlled write AC waveforms DC and AC parameters 45/70 ...
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DC and AC parameters Table 19. Asynchronous write and latch controlled write AC characteristics Symbol t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge) 1. The M58BW016F first data output is synchronized with the clock’s active edge, while the M58BW016D first data output is not synchronized with the ...
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DC and AC parameters Table 20. Synchronous burst read AC characteristics Symbol t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid t BHKH Clock Edge Burst Address Advance Low to Valid t BLKH Clock Edge ...
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... V= Valid output open drain output with an internal pull up resistor typically 300 k for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge. Figure 16. Synchronous burst read - burst address advance ...
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DC and AC parameters Figure 17. Reset, power-down and power-up AC waveforms - control pins low tVDHPH VDD, VDDQ Figure 18. Reset, power-down and power-up AC waveforms - control pins toggling ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 19. Power supply slope specification Voltage VDHH VDH 1. Please refer to the application note AN2601. Table 21. Power supply AC and DC characteristics Symbol V Minimum value of power supply DH V Maximum value ...
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... Package mechanical 8 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK packages. ECOPACK marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 23. PQFP80 - 80 lead plastic quad flat pack, package mechanical data Symbol millimeters Typ Min Max ...
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Package mechanical Figure 21. LBGA80 10 × × 10 active ball array pitch, package outline Drawing is not to scale. Table 24. LBGA80 10 × × ...
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... AEC Q001 & Q002 or equivalent. Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. M58 BW016D = ...
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... Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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... Data n 15h 2 number of bytes memory size 03h Device interface sync./async. 00h Organization sync./async. 00h n Page size in bytes, 2 00h 02h Bit7-0 = number of erase block regions in device 1Eh Number (n-1) of blocks of identical size ...
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Common Flash interface (CFI) Table 30. Extended query information Address Address offset A18-A0 (P)h 35h (P+1)h 36h (P+2)h 37h (P+3)h 38h (P+4)h 39h (P+5)h 3Ah (P+6)h 3Bh (P+7)h 3Ch (P+8)h 3Dh (P+9)h 3Eh (P+A)h 3Fh 58/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...
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... Program Error (1) NO Program to Protect Block Error Flowcharts Program Command: – write 40h – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) while invalid error: – error handler Program error: – ...
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... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Program completed Read Memory Array Command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume erasure – if the program operation completed then this is not necessary ...
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... NO Erase to Protected Block Error Flowcharts Erase Command: – write 20h – write Block Address (A11-A18) & D0h (memory enters read status state after the Erase command) do: – read status register ( must be toggled) if Erase command given execute suspend erase loop while invalid error: – ...
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... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Erase completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program/Erase Resume command: – write D0h to resume the Erase operation – ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 26. Power-up sequence followed by synchronous burst read Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '1' Set Burst Configuration Register Command: – ...
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Flowcharts Figure 27. Command interface and program/erase controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B 64/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB NO YES NO 70h YES READ ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 28. Command interface and program/erase controller flowchart ( 60h YES NO FFh SET BCR SET_UP YES NO 03h YES Flowcharts D AI03836b 65/70 ...
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Flowcharts Figure 29. Command interface and program/erase controller flowchart ( READ STATUS READ ARRAY 66/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE ...
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 30. Command interface and program/erase controller flowchart ( READ STATUS READ ARRAY YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS Flowcharts C PROGRAM READY NO NO READ B0h ...
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Revision history 10 Revision history Table 31. Document revision history Date Version January-2001 05-Jun-2001 15-Jun-2001 17-Jul-2001 17-Dec-2001 17-Jan-2002 30-Aug-2002 4-Sep-2002 13-May-2003 16-Oct-2003 03-Mar-2005 06-Sep-2005 3-Mar-2006 16-Jun-2006 68/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 01 First Issue. 02 Major rewrite and restructure. 03 ...
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... Added: information on data retention and reliability level 3 below Table 7: Burst configuration Figure 13: Synchronous burst read (data valid from ‘n’ clock rising 16 Modified: note 2 below Table 7: Burst configuration register Table 25: Ordering information Minor text changes. 17 Applied Numonyx branding. Revision history Changes Figure 21 and Table 24). read. characteristics, I added. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...