M58BW016FB7T3T NUMONYX, M58BW016FB7T3T Datasheet - Page 23

• Manufacturer Part Number: M58BW016FB7T3T
• Description: IC FLASH 16MBIT 70NS 80PQFP
• Manufacturer: NUMONYX

Specifications of M58BW016FB7T3T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (512K x 32)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: M58BW016FB7T3TCT

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Burst configuration register
The burst configuration register is used to configure the type of bus access that the memory
will perform.
The burst configuration register is set through the command interface and will retain its
information until it is re-configured, the device is reset, or the device goes into reset/power-
down mode. The burst configuration register bits are described in
selection of the burst length, burst type, burst X and Y latencies and the read operation.
Refer to
Read select bit (M15)
The read select bit, M15, is used to switch between asynchronous and synchronous bus
read operations. When the read select bit is set to ’1’, bus read operations are
asynchronous; when the read select bit is set to ’0’, bus read operations are synchronous.
On reset or power-up the read select bit is set to’1’ for asynchronous accesses.
X-Latency bits (M14-M11)
The X-Latency bits are used during synchronous bus read operations to set the number of
clock cycles between the address being latched and the first data becoming available. For
correct operation the X-Latency bits can only assume the values in
configuration
Table 8: Burst type definition
Y-Latency bit (M9)
The Y-Latency bit is used during synchronous bus read operations to set the number of
clock cycles between consecutive reads. The Y-Latency value depends on both the X-
Latency value and the setting in M9.
When the Y-Latency is ‘1’ the data changes each clock cycle; when the Y-Latency is ‘2’ the
data changes every second clock cycle. See
Table 8: Burst type definition
clock frequency.
Valid data ready bit (M8)
The valid data ready bit controls the timing of the valid data ready output pin, R. When the
valid data ready bit is ’0’ the valid data ready output pin is driven Low for the active clock
edge when invalid data is output on the bus. When the valid data ready bit is ’1’ the valid
data ready output pin is driven Low one clock cycle prior to invalid data being output on the
bus.
Burst type bit (M7)
The burst type bit is used to configure the sequence of addresses read as sequential or
interleaved. When the burst type bit is ’0’ the memory outputs from interleaved addresses;
when the burst type bit is ’1’ the memory outputs from sequential addresses. See
Burst type
each mode.
Figure 4
definition, for the sequence of addresses output from a given starting address in
register. The X-Latency bits should also be selected in conjunction with
and
Figure 5
to ensure valid settings.
for valid combinations of the Y-Latency, the X-Latency and the
for examples of synchronous burst configurations.
Table 7: Burst configuration
Table
Table 7: Burst
7. They specify the
register, and
Bus operations
Table 8:
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