M58BW32FB5ZA3F NUMONYX, M58BW32FB5ZA3F Datasheet
M58BW32FB5ZA3F
Specifications of M58BW32FB5ZA3F
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M58BW32FB5ZA3F Summary of contents
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... Electronic signature – Manufacturer code: 0020h – Top device codes: M58BW32FT: 8838h M58BW16FT: 883Ah – Bottom device codes: M58BW32FB: 8837h M58BW16FB: 8839h Automotive device grade 3: – Temperature: – – Automotive grade certified Rev 6 M58BW16F M58BW32F LBGA 40 to 125 °C 1/87 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Valid Data Ready bit (M8 3.3.6 Wrap Burst bit (M3 3.3.7 Burst Length bit (M2-M0 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 Block Erase command ...
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PEN Status (bit ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Program and Erase commands are written to the command interface of the memory. An on- chip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register ...
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... Finally, the M58BWxxF features a 64-bit unique device identifier (UID) which is programmed by Numonyx on the production line unique for each die and can be used to implement cryptographic algorithms to improve security. Information is available in the CFI area (see Table 32: M58BW16F extended query The memory is offered in PQFP80 ( mm) and LBGA80 (1.0 mm pitch) packages and it is supplied with all the bits erased (set to ’ ...
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Figure 1. Logic diagram (1) A0-Amax E K PEN DDQ V DDQIN DQ0-DQ31 M58BW16F M58BW32F SSQ AI13224b 9/87 ...
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Table 1. Signal names Signal name (1) A0-Amax Address inputs DQ0-DQ7 Data input/output, command input DQ8-DQ15 Data input/output, Burst Configuration Register DQ16-DQ31 Data input/output B Burst Address Advance input E Chip Enable input G Output Enable input K Burst Clock ...
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Figure 2. LBGA connections (top view through package A15 A14 B A16 A13 C A17 A18 D DQ3 DQ0 E V DDQ DQ4 F V SSQ DQ7 G V DDQ DQ8 H DQ13 DQ12 J DQ15 DQ14 ...
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Figure 3. PQFP connections (top view through package) DQ16 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 12/87 1 M58BW16F 12 ...
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Block protection The M58BWxxF features four different levels of block protection. Write Protect pin, WP, - When WP is Low, V configured in the Block Protection Configuration Register is activated. The Block Protection Configuration Register is volatile. Any combination ...
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Table 2. M58BW32F top boot block addresses # Size (Kbit) 73 128 72 128 71 128 70 128 512 60 512 59 512 58 512 57 512 56 512 55 512 ...
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Table 2. M58BW32F top boot block addresses (continued) # Size (Kbit) 35 512 34 512 33 512 32 512 31 512 30 512 29 512 28 512 27 512 26 512 25 512 24 512 23 512 22 512 21 ...
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Table 3. M58BW32F bottom boot block addresses # ...
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Table 3. M58BW32F bottom boot block addresses (continued) # Size (Kbit) 35 512 34 512 33 512 32 512 31 512 30 512 29 512 28 512 27 512 26 512 25 512 24 512 23 512 22 512 21 ...
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Table 4. M58BW16F top boot block addresses # 38 37 ( ...
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Table 5. M58BW16F bottom boot block addresses # Size (Kbit) 38 512 37 512 36 512 35 512 34 512 33 512 32 512 31 512 30 512 29 512 28 512 27 512 26 512 25 512 24 512 ...
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... Address inputs (A0-Amax) Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. The Address inputs are used to select the cells to access in the memory array during Bus operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. Chip Enable must be Low when selecting the addresses ...
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... Latch Enable, L). 2.7 Reset/Power-down (RP) The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-down Low, V inhibited to protect data, the command interface and the Program/Erase controller are reset. The Status Register information is cleared and power consumption is reduced to the ...
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... Valid Data Ready (R) The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. ...
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Supply voltage (V The supply voltage, V from the V pin, including the Program/Erase controller. DD 2.15 Output supply voltage (V The output supply voltage, V Program and Erase) used for DQ0-DQ31 when used as outputs. 2.16 Input supply ...
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... Asynchronous Latch Controlled Bus Read Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses ...
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... Asynchronous Latch Controlled Bus Write Asynchronous Latch Controlled Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock Don’t care during Bus Write operations. ...
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... Configuration Register to ‘1’ (see 3.1.8 Reset/Power-down The memory is in Reset/Power-down mode when Reset/Power-down, RP power consumption is reduced to the standby level (I impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs. In this mode the device is write protected and both the Status and the Burst Configuration Registers are cleared ...
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... Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance Low. ...
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... Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power- down mode ...
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... The Burst Length bits set the maximum number of double-words that can be output during a Synchronous Burst Read operation. Burst lengths are available. Table 8: Burst Configuration Register that the memory accepts Burst Read operation (no wrap) has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output ...
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Table 8. Burst Configuration Register Bit Description M15 Read Select M14 Standby Disable M13-M11 X-Latency M10 M9 Y-Latency M8 Valid Data Ready M7 (3) M6 M5-M4 M3 Wrapping 30/87 Value 0 Synchronous Burst Read 1 Asynchronous Read (default at power-on) ...
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Table 8. Burst Configuration Register (continued) Bit Description M2-M0 Burst Length 1. X latencies can be calculated as: (t AVQV number from the clock period and t K calculation latencies can be calculated ...
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Table 9. Burst type definition Start address Figure 4. Example burst configuration X-1-1 ADD VALID L DQ 3-1-1-1 DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ ...
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... Read Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the common Flash interface memory area. ...
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... Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. ...
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... Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. ...
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... Status Register bits 4 and 5 are set to ‘1’ and the operation will abort without affecting the data in the memory array. A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation the memory will only accept the Read Status Register and the Program/Erase Suspend commands. All other commands are ignored. If PEN operation aborts and the Status Register PEN bit (bit 3) is set to '1' ...
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... Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase controller has paused; no other commands will be accepted until the Program/Erase controller has paused. After the Program/Erase controller has paused, the memory will continue to output the Status Register until another command is issued. ...
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... Burst Configuration Register content written, and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to ‘1’. Once the command is issued the memory returns to Read mode Read Memory Array command had been issued. ...
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... Table 10. Commands Command Read Memory Array 2 Write (2) Read Electronic Signature 2 Write Read Status Register 1 Read Query 2 Write Clear Status Register 1 Block Erase 2 Erase All Main Blocks 2 any block 2 Program OTP block 2 Write to Buffer and Program N+4 Write AAh E8h Write Program/Erase Suspend ...
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... Program/Erase cycles (per block –40 to 125 ° The minimum effective erase time is defined as the minimum time required between the last Erase Resume command and the next Erase Suspend command for the internal Flash memory Program/Erase controller to be able to execute its algorithm. 40/87 Device Amax-A0 ...
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... When the Erase Suspend Status bit is set to ‘0’, the Program/Erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘ ...
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... Erase Status (bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to ‘ ...
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... When the Program Suspend Status bit is set to ‘0’, the Program/Erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘ ...
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Table 13. Status Register bits Bit 7 Program/Erase Controller Status 6 Erase Suspend Status 5 Erase Status 4 Program Status, 3 PEN Status bit 2 Program Suspend Status Erase/Program in a protected 1 block 0 Reserved 44/87 Name Logic level ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 14. ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the ...
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Table 17. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT ° MHz Sampled only, not 100% tested. Table 18. DC characteristics Symbol Parameter I Input Leakage current ...
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Figure 7. Asynchronous Bus Read AC waveforms A0-A19 DQ0-DQ31 Figure 8. Asynchronous Latch Controlled Bus Read AC waveforms A0-A19 L tLHLL E G DQ0-DQ31 48/87 tAVAV VALID tAVQV tEHLX tELQX tELQV tGLQX tGLQV OUTPUT See also ...
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Figure 9. Asynchronous Chip Enable Controlled Bus Read AC waveforms A0-A19 VALID DQ0-DQ31 Figure 10. Asynchronous Address Controlled Bus Read AC waveforms A0-A19 DQ0-DQ31 tLHAX tGLQX tGLQV tELQX tELQV OUTPUT See also Page Read ...
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Table 19. Asynchronous Bus Read AC characteristics Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV t Address Transition to Output Transition AXQX Chip Enable High to Latch Enable t EHLX Transition t Chip ...
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Figure 11. Asynchronous Page Read AC waveforms A0-A1 DQ0-DQ31 Table 20. Asynchronous Page Read AC characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings see Table 19: Asynchronous ...
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Figure 12. Asynchronous Write AC waveforms 52/87 ...
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Figure 13. Asynchronous Latch controlled Write AC waveforms 53/87 ...
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Table 21. Asynchronous Write and Latch controlled Write AC characteristics Symbol Parameter t Address Valid to Address Valid AVAV t Address Valid to Latch Enable High AVLH t Address Valid to Latch Enable Low AVLL t Address Valid to Write ...
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Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’ clock rising edge) 55/87 ...
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Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’ clock rising edge) 56/87 ...
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Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid from ’n’ clock rising edge) 57/87 ...
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Figure 17. Synchronous Burst Read (data valid from ’n’ clock rising edge tKHQV DQ0-DQ31 Q0 SETUP Note: n depends on Burst X-Latency 1. For set up signals and timings see Synchronous Burst Read. Figure 18. Synchronous Burst Read ...
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Figure 19. Synchronous Burst Read - Burst Address Advance K VALID A0-A19 L DQ0-DQ31 G B Figure 20. Clock input AC waveform tGLQV tBLKH tBHKH tKHKL tKLKH Q2 AI03650 ai13286 59/87 ...
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Table 22. Synchronous Burst Read AC characteristics Symbol Parameter f Clock frequency t Address Valid to Valid Clock Edge AVKH t Clock High time KHKL t Clock Low time KLKH Burst Address Advance High to Valid t BHKH Clock Edge ...
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Figure 21. Power supply slope specification Voltage VDHH VDH 1. Please refer to the application note AN2601. Table 23. Power supply AC and DC characteristics Symbol V Minimum value of power supply ( Maximum value of power supply ...
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Figure 22. Reset, Power-down and Power-up AC waveforms - Control pins Low Hi tVDHPH VDD, VDDQ Figure 23. Reset, Power-down and Power-up AC waveforms - Control pins toggling Hi-Z R ...
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Table 24. Reset, Power-down and Power-up AC characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL t Reset/Power-down High to Latch Enable Low PHLL (1) t Reset/Power-down High to Output Valid PHQV t Reset/Power-down High to Write Enable Low ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 24. LBGA80 10 × ...
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Table 25. LBGA80 10 × × 10 active ball array pitch, package mechanical data millimeters Symbol Typ Min 0.60 D 10.00 D1 7.00 ddd E 12.00 E1 9.00 e ...
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Figure 25. PQFP80 - 80 lead plastic quad flat pack, package outline Nd QFP-B 1. Drawing is not to scale. Table 26. PQFP80 - 80 lead plastic quad flat pack, package mechanical data Symbol Typ 2.80 b ...
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... Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. range for 45 ns speed class ...
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... End error is found, the Status Register must be cleared before further P/E operations. 68/87 Program command: – write 40h, Address AAh – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) while ...
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... B0h – write 70h do: – read status register while Program completed Program Complete Read Memory Array command: – write FFh – one or more data reads from other blocks Program Erase Resume command: Write FFh – write D0h to resume programming – ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 70/87 Erase command: – write 20h, Address 55h – write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command) NO do: – read status register ( must be toggled) ...
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... Erase Complete (b6 = Erase Suspend status bit) The device returns to Read mode as normal (as if the Program/Erase Suspend was not issued). Write FFh Read Memory Array command: – Write FFh – One or more data reads from other blocks Read Data Program/Erase Resume command: – ...
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Figure 30. Power-up sequence followed by Synchronous Burst Read Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read 72/87 BCR bit 15 = '1' Set Burst Configuration Register command: – write 60h – ...
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Figure 31. Command interface and Program/Erase controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE YES READ CFI ERASE COMMAND ERROR READ STATUS 70h YES READ NO 20h STATUS YES ERASE 40h ...
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Figure 32. Command interface and Program/Erase controller flowchart ( 48h YES TP 78h PROGRAM SET_UP YES F TP UNLOCK SET_UP G 74/ 60h YES NO FFh SET BCR SET_UP YES NO 03h YES D AI03836 ...
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Figure 33. Command interface and Program/Erase controller flowchart ( READ STATUS READ ARRAY YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE YES READY NO NO READ B0h ...
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Figure 34. Command interface and Program/Erase controller flowchart ( YES READ STATUS READ ARRAY 76/87 YES YES PROGRAM SUSPENDED YES 70h NO NO YES READ D0h STATUS C PROGRAM READY NO NO READ B0h STATUS YES PROGRAM SUSPEND ...
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Figure 35. Command interface and Program/Erase controller flowchart ( PROGRAM YES NO READ READY STATUS UNLOCK YES NO READ READY STATUS AI03839 77/87 ...
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... Offset 19h defines A which points to the alternate algorithm extended query address table. 78/87 Table 28, Table Sub-section name Manufacturer code Numonyx Device code Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the primary algorithm (optional) ...
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Table 29. CFI - Query address and data output Address A0-Amax 10h 51h 11h 52h 12h 59h 13h 14h 35h (M58BW16F) 15h 39h (M58BW32F) 16h 17h 18h 19h 1Ah 1. The byte address and the x 16 ...
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... Data Description n 15h 2 number of bytes memory size 03h Device interface sync./async. 00h Organization sync./async. 00h Maximum number of byte in multi-byte program = 2 00h 02h Bit7-0 = number of Erase Block regions in device 1Eh Number (n-1) of Erase Blocks of identical size; n=31 31 blocks ...
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Table 32. M58BW16F extended query information Address Address offset Data (hex) Amax-A0 (P)h 35h (P+1)h 36h (P+2)h 37h (P+3)h 38h (P+4)h 39h (P+5)h 3Ah (P+6)h 3Bh (P+7)h 3Ch (P+8)h 3Dh (P+9)h 3Eh (P+A)h-(P+D)h 3Fh-42h (P+13)h-(P+40)h 48h-7Fh (P+41)h 80h xxxx xxxxh ...
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... Data Description n 15h 2 number of bytes memory size 03h Device interface sync./async. 00h Organization sync./async. 00h Maximum number of byte in multi-byte program = 2 00h 02h Bit7-0 = number of Erase Block regions in device 1Eh Number (n-1) of Erase Block regions of identical size; ...
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Table 34. M58BW32F extended query information Address Address offset Data (hex) Amax-A0 (P)h 39h 50 (P+1)h 3Ah 52 (P+2)h 3Bh 49 (P+3)h 3Ch (P+4)h 3Dh (P+5)h 3Eh (P+6)h 3Fh (P+7)h 40h (P+8)h 41h (P+9)h 42h (P+A)h-(P+D)h 43h-46h (P+13)h-(P+40)h 4Ch-7Fh (P+41)h ...
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Table 35. Protection register information Address M58BW16FT A0-Amax M58BW16FB 0x02 (P+E)h 0x02 0x01 (P+F)h 0xFE 0x01 (P+10)h 0xFE 0x0 (P+11)h 0x0 0x12 x256 0x12 84/87 Data Instruction M58BW32FT M58BW32FB Number of Protection 0x01 register field in JEDEC 0x01 ID space, ...
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Appendix C Block protection OTP protection The OTP protection is an user-enabled feature that permanently protects specific blocks, so called “OTP blocks”, against modify operations (program/erase available: on one specific 128-kbit parameter block in the M58BW32F- block 1 ...
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Revision history Table 36. Document revision history Date 09-Jun-2006 23-Nov-2006 01-Oct-2007 15-Jan-2008 86/87 Revision 1 Initial release. V signal renamed as PEN and PEN modified. Continuous burst and wrap options are not available, X-Latencies 7 and 8 removed (see ...
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... Table 36. Document revision history Date Revision 19-Mar-2008 5 Applied Numonyx branding. 3-August-2009 6 Minor text updates. Changes 87/87 ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...