RC28F128K3C115 Intel, RC28F128K3C115 Datasheet
RC28F128K3C115
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RC28F128K3C115 Summary of contents
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... Intel introduced the original device in 1997. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the lat- est datasheet before finalizing a design. ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... High Performance Page/Burst Modes...................................................................9 2.2 Single Chip Solution ..............................................................................................9 2.3 Packaging Options ..............................................................................................10 2.4 Product Highlights ...............................................................................................10 2.5 K3/K18 Block Diagram ........................................................................................11 2.6 Memory Map .......................................................................................................12 3.0 Package Information 3.1 Easy BGA Package.............................................................................................13 3.2 VF BGA for 64 Mbit and 128 Mbit Package ........................................................14 3.3 VF BGA for 256 Mbit Package ............................................................................15 4.0 Ballout and Signal Description 4 ...
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Output Disable ....................................................................................... 36 9.1.4 Standby .................................................................................................. 36 9.1.5 Reset ...................................................................................................... 36 9.2 Device Commands .............................................................................................. 37 10.0 Read Modes ................................................................................................................ 39 10.1 Asynchronous Page-Mode Read ........................................................................ 39 10.2 Synchronous Burst-Mode Read .......................................................................... ...
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Read Query/CFI ..................................................................................................58 14.4 STS Configuration (Easy BGA package ONLY)..................................................58 Appendix A Write State Machine (WSM) Appendix B Common Flash Interface Appendix C Flowcharts ............................................................................................................... 70 Appendix D Additional Information Appendix E Ordering ...
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Revision History Date of Revision Revision 08/22/01 -001 09/24/01 -002 09/27/01 -003 02/22/02 -004 06/17/02 -005 06/11/03 -006 12/01/03 -007 5/19/04 -008 2/1/05 -009 6 Description Original Version Corrected Typographical Errors in 11.0 AC ...
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... Introduction This document contains information pertaining to the Intel StrataFlash (K3/K18) device. The purpose of this document is to describe the features, operations and specifications of these devices. 1.1 Nomenclature 3 Volt core Volt I/O: V CCQ 1.8 Volt I/O: ...
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Conventions 0x: Hexadecimal prefix 0b: Binary prefix k (noun): 1,000 M (noun): 1,000,000 Byte: 8 bits Word: 16 bits Kword: 1,024 words Kb: 1,024 bits KB: 1,024 bytes Mb: 1,048,576 bits MB: 1,048,576 ...
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... Intel StrataFlash the K3/K18 utilizes reliable and proven two-bit-per-cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. This is the third generation of Intel's multi-level cell (MLC) technology, manufactured on 0.18 µm lithography, making it the most widely used and proven MLC product family on the market ...
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... BGA package provides SOP reliability and long-term footprint compatibility and cost in a chip scale package size. The VF BGA and SCSP offer small footprints for wireless applications. Manufactured on the Intel 0.18-micron process technology, Intel StrataFlash unprecedented value and performance and reliability. 2.4 ...
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... K3/K18 Block Diagram Figure 1. K3/K18 Device Memory Block Diagram V CCQ WAIT Y-Decoder Input AMAX : AMIN Buffer CLK Address ADV# Latch Address Counter Datasheet CCQ Output Input Buffer Buffer Query Identifier Register Status Register Read State ...
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... Mbit device contains 128 blocks and a 256 Mbit device contains 256 blocks. Flash cells within a block are organized by rows and columns. A block contains 512 rows by 128 words. The words on a row are divided into 16 eight-word groups. (See Figure 2. K3/K18 Device Memory Map 12 0xFFFFFF ...
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Package Information 3.1 Easy BGA Package Figure 3. Easy BGA Package Drawing Ball A1 Corner Top View - ...
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Table 1. Easy BGA Package Dimensions (Sheet Seating Plane Coplanarity Corner to Ball A1 Distance Along D (64/128/256 Mb) Corner to Ball A1 Distance Along E (64/128 Mb) Corner to Ball ...
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Table 2. VF BGA Package (64 Mb and 128 Mb) Dimensions (Sheet Ball (Lead) Width Package Body Width (64 Mb) Package Body Width (128 Mb) Package Body Length (64 Mb, 128 ...
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Table 3. VF BGA (256 Mb) Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 ...
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Ballout and Signal Description The K3/K18 device is available in a 64-ball Easy BGA package for the 64-, 128-, and 256 Mbit densities. See Figure This device is also available in a 56-ball ...
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VF BGA Package for 64- and 128-Mbit Density (0.75 mm Ball Pitch) Figure 7. 56-Ball VF BGA Package 0.75 mm Ball Pitch (for 64- and 128-Mb Densities ONLY ...
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VF BGA for 256-Mbit Density Package Figure 8. 79-Ball VF BGA Package for 256-Mbit Density A11 A12 C A13 D A15 E VCCQ ...
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... DO NOT USE: Do not use this ball. This ball should not be connected to any power supplies, DU — signals or other balls and must be left floating. NC — NO CONNECT: No internal connection; can be driven or floated. RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device RFU — functionality and enhancement. 20 Name and Function and A values ...
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Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings The absolute maximum ratings are shown in Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings ...
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Electrical Specifications 6.1 DC Current Characteristics Table 6. DC Current Characteristics CCQ Sym Parameter I Input Load Current LI I Output Leakage Current LO 64 Mbit, 128 Mbit V CC ...
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Table 7. DC Voltage Characteristics V V Sym Parameter Input Low V IL Voltage Input High V IH Voltage Output Low V OL Voltage Output High V OH Voltage V Lock-Out during PEN V ...
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AC Characteristics 7.1 Read Operations Table 8. AC Read Characteristics (Sheet Num Sym Asynchronous Specifications R1 t Read cycle time AVAV R2 t Address to output delay AVQV R3 t ...
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Table 8. AC Read Characteristics (Sheet Num Sym R104 t ADV# pulse width low VLVH R105 t ADV# pulse width high VHVL Address hold from ADV# R106 t VHAX high R108 ...
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Figure 9. Single Word Asynchronous Read Waveform Address [A] ADV# CE# [E} OE# [G] WAIT [T] Data [D /Q] RST# [P] Figure 10. Page Mode Read Waveform A[Max:3] [A] A[2:0] R105 R105 ADV# [V] ...
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Figure 11. Single Word Burst Read Waveform CLK [C] Address [A] ADV# [V] CE# [ WAIT [T] Data [D/Q] NOTE: WAIT (shown active low) can be configured to assert either ...
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Figure 12. 8 Word Synchronous Burst Read Waveform CLK Address [A] ADV# CE# [E] OE# [G] WAIT [T] DATA [D/Q] NOTES: 1. Section 4.9.13, “First Access Latency Count (CR.11-13)” on page 38 during the ...
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Write Operation Table 9. Write Characteristics Num Sym RST# high recovery to WE PHWL low W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH ...
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Figure 14. Write to Write Waveform Address [A] CE# [E} WE# [W] OE# [G] Data [D/Q] RST#/ RP# [P] Figure 15. Asynchronous Read to Write Waveform Address [A] CE# [E} OE# [G] WE# [W] ...
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Figure 16. Asynchronous Write to Read Waveform Address [A] CE# [E} WE# [W] OE# [G] Data [D/Q] RST # [P] 7.3 Block Erase and Program Operation Performance Table 10. Block Erase and Program Operation ...
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AC Test Conditions Figure 17. AC Input/Output Reference Waveform V CCQ Input V 0V NOTE: AC test inputs are driven /2. Input rise and fall times (10% to 90%) ...
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... After return from reset, the flash device defaults to asynchronous page mode. If RST# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Operation Waveforms” on page 34 ...
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Reset Operation Figure 19. Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) ...
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... To perform a bus read operation, CE# and OE# must be asserted. CE# is the device-select control; when active, it enables the flash memory device. OE# is the data-output control; when active, the addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RST# must be de-asserted. See Section 7.1, “ ...
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... If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Intel reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU ...
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... Code Address Code Data Query Code Query Code Read Address Data Address with Status Read Block Register Data Address of Data to be Write memory to be programed programed Number of Address words to be Write within Block written to buffer Address Write 0xD0 within Block Address ...
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Table 15. Command Bus Definitions (Sheet Bus Command Cycles Read Configuration 2 Register Lock Block 2 Unlock Block 2 Lock-Down Block 2 STS 2 Protection 2 Program Lock Protection 2 Program ...
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... D[15:0] after a minimum delay. (See In asynchronous page mode, one of 16 eight-word groups are “sensed” simultaneously from the flash memory and loaded into an internal page buffer. After the initial access delay, the first word out of the data buffer corresponds to the initial address, A[A ...
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... Synchronous Burst-Mode Read Since asynchronous page mode is the default read mode following a device power-up or reset, the appropriate bits in the RCR must be set before synchronous burst mode reads of the flash memory can occur. See Section 10.3, “Read Configuration Register” on page 40 after configuring the RCR not necessary to issue the Read Array command (0xFF) before performing a synchronous burst-mode read ...
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Table 16. Read Configuration Register (Sheet 14:11 Latency Count (LC[3:0]) 10 Wait Polarity (WP) 9 Data Hold (DH) 8 Wait Delay (WD) 7 Burst Sequence (BS) 6 Clock Edge (CE) 5:3 ...
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Figure 20. First-Access Latency Count CLK [C] Address [A] Address ADV# [V] DQ [D/Q] 15-0 DQ [D/Q] 15-0 DQ [D/Q] 15-0 DQ [D/Q] 15-0 DQ [D/Q] 15-0 DQ [D/Q] 15-0 DQ [D/Q] 15-0 DQ ...
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... D[15:0] for one or two clock cycles. When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock cycle. (See processor’s data setup time and the flash memory’s clock-to-data output delay should be considered in determining whether to hold output data for one or two clocks. ...
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... Burst Length BL[2:0] selects the linear burst length for all synchronous burst reads of the flash memory. The burst length can be configured 8-word or a 16-word burst. Once a burst cycle begins, the device will output synchronous burst data until it reaches the end of the burstable address space. ...
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... During programming, the Write State Machine executes a sequence of internally-timed events that program the desired data bits and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to ones only by erasing the block. ...
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... A misaligned starting address will result in a doubling of the total program time. After the last data is written to the write buffer, the Write-to-Buffer Confirm command is issued. The Write State Machine begins to copy the write buffer contents to the flash memory array command other than the Write-to-Buffer Confirm command is written to the device, a command sequence error will occur and Status Register bits SR4, SR5 and SR7 will be set ...
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... Host programmer bus cycles fill the device write buffer, followed by a status check of SR.0 to determine when the data from that page has completed programming into sequential flash memory locations. Following the buffer-to-flash programming sequence, the WSM increments internal addressing to automatically select the next 32-word array boundary. This aspect of Buffered-EFP saves programming equipment address-bus setup overhead ...
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... FFFFh. The responsibility to manage this falls within the programming equipment, not the customer data file. Data words from the write buffer are directed to sequential memory locations in the array, programming takes up where the last page sequence left off. The host programming system must poll SR ...
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SR.0=1 indicates that the WSM is still busy. The host system may check full status for errors at any time, but it is only necessary ...
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... Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address within the block. A block erase operation can be ...
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Erase Resume To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The Resume command can be written to any device address. When a program operation is nested within an ...
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... Block Locking Operations Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up locked to protect array data from being altered during power transitions. Any block can be locked or unlocked without latency. Locked blocks cannot be programmed or erased ...
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Block Lock All blocks default to the locked state after initial power-up or reset. An unlocked block can be locked by issuing the Block Lock command sequence. This sets the block lock status ...
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... The device includes 17 128-bit Protection Registers, PR16 through PR0, which can be used to increase system security or to provide identification capabilities. PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for the customer to program ...
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... To lock a Protection Register, program the corresponding bit in the PR Lock Register by issuing the Program PR Lock Register command followed by the desired PR Lock Register data. Bit Lock Register 0 is already programmed at the Intel factory and locks PR0[63:0]. Bit Lock Register 0 can be programmed by the user to lock the user-programmable portion of Protection Register 0, namely PR0[128:64] ...
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Special Modes This section describes in details how to read the status, ID and CFI registers. This sections also details how to configure the STS signal. 14.1 Read Status Register The status of ...
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Table 20. Status Register Description (Sheet Status Register (SR) 2 Program Suspend 1 Block-Locked Error (LE) 0 Buffered-EFP Status (PS) 14.1.1 Clear Status Register The Clear Status Register command clears the ...
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... DQ5 DQ4 DQ3 Reserved Used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. Used to generate a system interrupt pulse when any flash device in an array has completed a block erase. Helpful for reformatting blocks after file system free space reclamation or “cleanup.” ...
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Appendix A Write State Machine (WSM) A.1 Nomenclature Table 23. Arrangement Of Next State Table Pages Note: Numbered notes referenced in superscript can be found at the end of the last table. Datasheet Next ...
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Table 24. Next State Table Part A Data Current State SR7 SR0 When Read Read Array 1 0 Array Read Status 1 0 Status Read Config 1 0 Config Read Query 1 0 CFI ...
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Table 24. Next State Table Part A Data Current State SR7 SR0 When Read BEFP (busy Status BEFP Exit (Busy Status BEFP Exit 1 0 Status Write to Buffer 1 ...
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Table 25. Next State Table Part B Current State SR7 SR0 Data When Read Read Array 1 0 Array Read Status 1 0 Status Read Config 1 0 Config Read Query 1 0 CFI ...
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Table 25. Next State Table Part B Current State SR7 SR0 Data When Read BEFP (busy Status BEFP Exit 0 1 Status (Busy) BEFP Exit 1 0 Status Write to Buffer 1 ...
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... BA = The beginning location of a Block Address (e.g., 010000h is the beginning location of block 1 when the block size is 64 Kword). 3. Offset 15 defines “P” which points to the Primary Intel - specific Extended Query Table. B.2 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...
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Table 27. CFI Identification Offset Length 10h 3 13h 2 15h 2 17h 2 19h 2 B.3 System Interface Information The following tables give information on the power supplies and the program and erase ...
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B.4 Device Geometry Definition The following tables give critical details provided by CFI when the software requests flash device geometry information such as the size of the device, types of read interfaces, program buffer ...
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B.5 Primary Vendor Specific Extended Query Table Certain flash features and commands are optional. The Primary Vendor Specific Extended Query Table specifies this and other similar information. Table 30. Primary Vendor Specific Extended Query ...
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Table 30. Primary Vendor Specific Extended Query Table (1) Offset Length P=31h (P+A)h 2 (P+B)h (P+C)h 1 (P+D)h 1 Table 31. Protection Register Information (1) Offset Length P=31h (P+E)h 1 (P+F)h, (P+10)h, 4 (P+11)h, ...
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Table 32. Burst/Page Read Information (1) Offset Length P=31h (P+1D)h 1 (P+1E)h 1 (P+1F)h 1 (P+20)h 1 Datasheet Description(Optional Flash Features and Commands) Page Mode Read Capability n bits 0-7=”n” such that 2 HEX ...
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Appendix C Flowcharts Figure 25. Write to Buffer Flowchart Start Device Supports Buffer Writes? Yes Set Time-out or Loop Counter Get Next Target Address Issue Write to Buffer Command 0xE8 and Block Address Read ...
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Figure 26. Word Programming Flowchart Start Write 0x40, Address Write Data and Address Read Status Register 0 SR Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Figure 27. Program Suspend/Resume Flowchart Start Write 0xB0 Read Status Register Write 0xFF Read Array Data Done No Reading Yes Write 0xD0 Program Resumed 72 Bus ...
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Figure 28. Buffered Enhanced Factory Programming Procedure Flowchart BEFP Setup Start Unlock Block Write 80h Address = WA 0 Write D0h Address = WA 0 BEFP Setup time Read Status Register SR.7=0=Y BEFP Setup ...
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Figure 29. Block Erase Flowchart Start Write 0x20 Block Address Write 0xD0 and Block Address Read Status Register No 0 SR.7 = Suspend Erase 1 Full Status Check if Desired Block Erase Complete FULL ...
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Figure 30. Erase Suspend/Resume Flowchart ERASE SUSPEND/RESUME PROCEDURE Start Write 0xB0 Write 0x70 Read Status Register Read or Read Program Write? Read Array Program No Data ...
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Figure 31. Protection Register Programming Flowchart Start Write 0xC0 (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register No SR Yes Full Status Check if Desired Program Complete FULL STATUS ...
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Figure 32. Block Lock Operations Flowchart Start Lock Setup Write 60h Block Address Lock Confirm Write 01,D0,2Fh Block Address Read ID Plane Write 90h Read Block Lock Status Locking No Change? Yes Read Array ...
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... Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http:// developer ...
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... Table 33. Valid Combinations Density 64 Mbit 128 Mbit 256 Mbit Datasheet BGA Easy BGA GE28F640K3C110 RC28F640K3C110 GE28F640K18C110 RC28F640K18C110 GE28F128K3C115 RC28F128K3C115 GE28F128K18C115 RC28F128K18C115 GE28F256K3C120 RC28F256K3C120 GE28F256K18C120 RC28F256K18C120 115 Access Speed (ns) 64 Mbit = 110 128 Mbit = 115 256 Mbit = 120 Process Identifier C = 0.18um Voltage Identifer (V ...
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Datasheet ...