TC58DVM72A1FT

Manufacturer Part NumberTC58DVM72A1FT
DescriptionIC FLASH 128MBIT 50NS 48TSOP
ManufacturerToshiba
TC58DVM72A1FT datasheet
 


Specifications of TC58DVM72A1FT

Format - MemoryFLASHMemory TypeFLASH - Nand
Memory Size128M (16M x 8)Speed50ns
InterfaceSerialVoltage - Supply2.7 V ~ 3.6 V
Operating Temperature0°C ~ 70°CPackage / Case48-TSOP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128-MBIT (16M
8 BITS/8M x 16BITS) CMOS NAND E
DESCRIPTION
The TC58DxM72x1xxxx is a 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable
2
Read-Only Memory (NAND E
PROM) organized as 528 bytes/264 words
dual power supplies (2.7 V to 3.6 V for V
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte/256-words increments. The Erase operation is implemented in a single block unit (16 Kbytes
528 bytes
32 pages/8k words + 256 words:264 words x 32 pages).
The TC58DxM72x1xxxx is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
TC58DxM72A1xxxx
Memory cell allay 528
32K
8
Register
528
8
Page size
528 bytes
Block size
(16K
512) bytes
Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Mode control
Serial input/output
Command control
Power supply
TC58DVM72x1xxxx
Vcc:
2.7V to 3.6V
Vccq:
2.7V to 3.6V
Program/Erase Cycles 1E5 cycle (with ECC)
Access time
Cell array to register 25 s max
Serial Read Cycle
50 ns min
Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 A max.
Package
TSOP I 48-P-1220-0.50 (Weight:0.53g typ)
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
2
PROM
32 pages
and 1.65 V to 1.95 V for V
). The device has a 528-byte/264-words
CC
CCQ
TC58DxM72F1xxxx
264 x 32k x 16
264 x 16
264 words
(8k + 256) words
TC58DAM72x1xxxx
2.7V to 3.6V
1.65V to 1.95V
1024 blocks. The device uses
512 bytes:
000707EBA1
2003-01-24 1/34

TC58DVM72A1FT Summary of contents

  • Page 1

    ... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2 PROM 32 pages and 1 ...

  • Page 2

    ... PIN ASSIGNMENT (TOP VIEW) TC58DVM72F1FT00 / TC58DAM72F1FT00 TC58DVM72A1FT00 / TC58DAM72A1FT00 x16 GND GND CLE CLE 16 ALE ALE PINNAMES I/O1 to I/O8 I/O port I/O9 to I/O16 I/O port (x16) CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect ...

  • Page 3

    ... Operating Temperature opr CAPACITANCE *(Ta =25° MHz) SYMB0L PARAMETER C Input IN C Output OUT * This parameter is periodically sampled and is not tested for every device. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Status register Address register Command register Control HV generator VALUE TC58DVxxxxx 0.6~4.6 0.6~4.6 0.6~4.6 0.6 V~V 0 ≦ ...

  • Page 4

    ... I Erasing Current CCO8 I Standby Current CCS1 I Standby Current CCS2 V High Level Output Voltage OH V Low Level Output Voltage Output Current TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 MIN 1004 MIN 2.7 2.7 2.0 0.3 * MIN 2.7 1. 0.78 CCQ 0 CONDITION CCQ OUT CCQ ...

  • Page 5

    ... RE Last Clock Rising Edge to Busy(in Sequential Read High to Ready(When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 MIN MAX ...

  • Page 6

    ... SYMBOL PARAMETER t Programming Time PROG Number of Programming Cycles on Same N Page t Block Erasing Time BERASE (1): Refer to Application Note (12) toward the end of this document. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 is greater than or equal to 100 ns. If the delay CEH signal stays Ready. t 100 ns CEH A 527 A Busy MIN TYP ...

  • Page 7

    ... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O1 to I/O8 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Setup Time Hold Time CLH ALH 2003-01-24 7/34 ...

  • Page 8

    ... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 to I/O8 Data Input Cycle Timing Diagram CLE ALS ALE WE I/O1 to I/O8 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 A16 ALH A17 to A23 : CLH 527 2003-01-24 8/34 ...

  • Page 9

    ... Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t t CLS CLH I/O1 70H * to I/ 70H represents the hexadecimal number TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 REH RHZ REA RHZ t CLS WHC CSTO t WHR CHZ REA RHZ t CEA ...

  • Page 10

    ... Read Operation using 00H Command 255 Read Cycle (1) Timing Diagram: When Interrupted by CE CLE t t CLS CLH ALH ALS ALE I/O1 00H I/O8 Column address Read Operation using 00H Command 255 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t t ALH AR2 REA D OUT A9 to A16 A17toA23 ALH AR2 ...

  • Page 11

    ... Read Operation using 01H Command 255 Read Cycle (3) Timing Diagram CLE t t CLS CLH ALH ALS ALE I/O1 50H to I/O8 Column address Read Operation using 50H Command N: 0 to15 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t t ALH A16 A17toA23 ALH A16 A17toA23 N * AR2 t t ...

  • Page 12

    ... ALE RE 00H A16 A17toA23 Column Page address address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A16 A17toA23 to I/O8 Column Page address address TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Page M access t R 256 256 Page M access 527 527 t R Page M 1 access ...

  • Page 13

    ... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA23 to I/O8 Column Page address address TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t R 512 512 512 Page M access 527 512 513 527 t R Page M 1 access : 2003-01-24 13/34 ...

  • Page 14

    ... Auto Block Erase Timing Diagram CLE t CLS t CLH CLS ALS ALH ALE I/O1 60H A9 to A16 A17toA23 to I/O8 Auto Block Erase Setup command TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t ALH t ALS 527 : not input data while data is being output BERASE D0H Erase Start Busy command ...

  • Page 15

    ... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 90H to I/O8 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 CEA t ALH t ALEA t REAID t REAID 00 98H Address Maker code input 73H Device code : 2003-01-24 15/34 ...

  • Page 16

    ... The Busy state ( during the Program, Erase and Read operations and will return to Ready state ( after completion of the operation. The output buffer for this signal is an open drain. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 ...

  • Page 17

    ... A23 * : A8 is automatically set to Low or High by a 00H command or a 01H command. I/O9-16 should be low when address is input. * I/O8 must be set to Low in the third cycle. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 I/O1 A page consists of 528 bytes in which 512 bytes are used I/O8 for main memory storage and 16 bytes are for redundancy or for other uses ...

  • Page 18

    ... Read Mode (3) 50 Reset FF Auto Program 10 Auto Block Erase 60 Status Read 70 ID Read 90 01 command isn’t implemented by x16. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE Output Select L Output Deselect TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 CLE ALE ...

  • Page 19

    ... Start-address input 256 M Select page N Figure 4. Read mode (2) operation TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Busy m A data transfer operation from the cell array to the register starts on the rising edge the third cycle (after the address information has been latched). The device will be in Busy state during this transfer period ...

  • Page 20

    ... When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal m=527,n=512 X16 : m=263,n=256 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Busy Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored ...

  • Page 21

    ... CLE ALE 70H I/O Figure 6. Status Read timing application example System Design Note: If the RY diagram, the Status Read function can be used to determine the status of each individual device. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 OUTPUT Fail: 1 Busy: 0 Not Protected Device 2 3 Busy 70H Status on ...

  • Page 22

    ... The device automatically executes the Erase and Verify operations Block Address Erase Start input: 2 cycles command TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 10 Status Read command completion of the operation. The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10H” command. ...

  • Page 23

    ... When a Reset (FFH) command is input during Read operation When a Status Read command (70H) is input after a Reset When two or more Reset commands are input in succession The second TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 FF t (max 10 s) RST FF t RST FF t (max 6 s) RST command is invalid, but the third Figure 8 ...

  • Page 24

    ... For the specifications of the access times t Table 6. ID Codes read out by ID read command 90H I/O8 I/O7 Maker code 1 0 Device code 0 1 I/O9 to I/O16 are “0” . TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t CEA t ALEA t REAID 98H Maker code , t and t refer to the AC Characteristics. ...

  • Page 25

    ... Execution command “10H” or the Reset command “FFH” command other than “10H” or “FFH” is input, the Program operation is not performed Command other than Programming cannot be executed. “10H” or “FFH” TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 reaches 2.5 V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 ...

  • Page 26

    ... Therefore, a Status Read during a Read operation is prohibited. However, when the Read command “00H” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Ex.) Random page program (Prohibition) ...

  • Page 27

    ... Add Start point C area 01H Add Start point B area To program region C only, set the start point to region C using the 50H command. 50H 80H 01H 80H TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Pointer 0 A (x16) 0~255 −−− (1) 00H 256~263 (2) 01H (3) 50H Figure 19 Pointer control ...

  • Page 28

    ... Ready/Busy pin ( A pull-up resistor needs to be used for termination because the circuit. V CCQ Device V SS Figure 21. This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 DIN Ready V CCQ R ...

  • Page 29

    ... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE 60 DIN (100 ns min) WW TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 29/34 ...

  • Page 30

    ... Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when WE goes High in the third cycle. Program operation CLE CE WE ALE I/O 80H TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Address input Figure 22. Address input Ignored Figure 23. Ignored Data input 2003-01-24 30/34 ...

  • Page 31

    ... A page can be divided into segments. Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1s 3rd programming Result Data Pattern 1 Note: The input data for unprogrammed or previously programmed page segments must be “1” TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 All 1s All 1s Data Pattern 2 All 1s Data Pattern 2 Figure 24. Data Pattern 3 ...

  • Page 32

    ... Block No erase operation is allowed to detected bad blocks TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 At the time of shipment, all data bytes in a Valid Block are FFh(x8) or FFFFh(x16). For Bad Block, all bytes are not in the FFh state(x8) or FFFFh state(x16). Please don’t perform erase operation to Bad Block. ...

  • Page 33

    ... Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shoetage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 DETECTION AND COUNTERMEASURE SEQUENCE ...

  • Page 34

    ... Package Dimensions Weight: 0.53g (typ.) TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Unit : mm 2003-01-24 34/34 ...