TC58DVM92A1FT Toshiba, TC58DVM92A1FT Datasheet
TC58DVM92A1FT
Specifications of TC58DVM92A1FT
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TC58DVM92A1FT Summary of contents
Page 1
... NC GND 32 I/ TC58DVM92A1FT00 512 bytes: 528 bytes 32 pages min 10 mA typ typ typ max. I/O port Chip enable Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy Ground input Power supply Ground 000707EBA1 ...
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... This parameter is periodically sampled and is not tested for every device. Status register Address register Command register Control HV generator 0 MHz) CONDITION OUT TC58DVM92A1FT00 Column buffer Column decoder Data register Sense amp Memory cell array VALUE UNIT 0.6 to 4.6 V 0.6 to 4 4.6 V) ...
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... MIN 2.7 2.0 0.3 * 0° to 70° CONDITION OUT mA OUT cycle cycle cycle cycle 0V 400 2 pin V 0 TC58DVM92A1FT00 TYP. MAX UNIT 4096 Blocks TYP. MAX UNIT 3 0.8 V MIN TYP. MAX UNIT 2 2003-01-10 3/44 ...
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... RE Last Clock Rising Edge to Busy (in Sequential Read High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load TC58DVM92A1FT00 MIN MAX UNIT NOTES ...
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... Block Erasing Time BERASE (1): Refer to Application Note (12) toward the end of this document. is greater than or equal to 100 ns. If the delay CEH signal stays Ready. t 100 ns CEH 527 A Busy t CRY MIN TYP. 200 2 200 2 TC58DVM92A1FT00 pin Busy signal is not output. MAX UNIT NOTES 1000 ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O1 to I/O8 Setup Time Hold Time CLH ALH t DH TC58DVM92A1FT00 : 2003-01-10 6/44 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE t I/O1 to I/O8 Data Input Cycle Timing Diagram CLE ALS ALE WE I/ A16 A17 to A24 TC58DVM92A1FT00 ALH A25 : CLH 527 2003-01-10 7/44 ...
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... RE t REA I/ Status Read Cycle Timing Diagram CLE t t CLS CLH I/O1 70H * to I/ 70H represents the hexadecimal number REH RHZ REA RHZ t CLS WHC CSTO t WHR TC58DVM92A1FT00 CHZ REA RHZ t CEA t CHZ RSTO RHZ Status output : 2003-01-10 8/44 ...
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... I/O8 Column address Read operation using 00H command 255 t t ALH AR2 REA A17 D D OUT A25 to A24 ALH AR2 REA A17 D D OUT A25 to A24 N N TC58DVM92A1FT00 t CEH t CRY OUT OUT OUT 527 CHZ RC t RHZ OUT OUT 2003-01-10 9/44 ...
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... ALS ALE I/O1 50H I/O8 Column address Read operation using 50H command ALH A17 A25 to A16 to A24 t ALH A17 A25 to A16 to A24 TC58DVM92A1FT00 t AR2 REA OUT OUT OUT 256 N 256 N 1 527 : AR2 REA OUT OUT OUT 512 N 512 N 1 527 : ...
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... ALE RE I/ 01H I/O8 A7 A16 Column address A17 A25 A24 Page t R address M Page M access A17 A25 to A24 Page t R 256 256 256 address Page M access TC58DVM92A1FT00 527 527 t R Page M 1 access : 527 527 t R Page M 1 access : 2003-01-10 11/44 ...
Page 12
... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/ 50H I/O8 A16 Column address A17 A25 to A24 Page t R 512 512 512 address Page M access TC58DVM92A1FT00 527 512 513 514 527 t R Page M 1 access : 2003-01-10 12/44 ...
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... ALH t ALS A17 A25 A24 527 : not input data while data is being output ALH WB BERASE D0H Erase Start Busy command : not input data while data is being output TC58DVM92A1FT00 t PROG 10H 70H Status output 70H Status output Status Read command 2003-01-10 13/44 ...
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... CLE t t CLS CLH ALH t ALS ALE I/ 80H A24 to /O8 to A16 (Page programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (dummy) Max 3 times repeat 31 times repeat Max 4 blocks programming TC58DVM92A1FT00 t DBSY 11H 80H to A7 Last district input 2 2003-01-10 14/44 ...
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... Do not input data while data is being output. times repeat 2 (Page programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (multi block program) Last district input 31 times repeat Max 4 blocks programming TC58DVM92A1FT00 t MBPBSY 15H 80H Max 3 times repeat 2003-01-10 15/44 ...
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... ALS ALE I/ 80H to A24 I/O8 to A16 not input data while data is being output. 3 (Last pages programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (dummy) Max 3 times repeat Max 4 blocks programming TC58DVM92A1FT00 t DBSY 11H 80H Last district input 2003-01-10 16/44 ...
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... I/O8 to A16 not input data while data is being output. 4 Max 3 times repeat (Last pages programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (true) Last district input Max 4 blocks programming TC58DVM92A1FT00 t PROG 10H 71H Status output 5 Status read 2003-01-10 17/44 ...
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... CS CLS ALS ALE I/ A17 to 60H A16 A24 to I/O8 Auto Block Erase Setup command Max 4 times repeat : not input data while data is being output ALH WB BERASE D0H A25 Erase Start Busy command TC58DVM92A1FT00 71H Status output Status Read command 2003-01-10 18/44 ...
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... I/O1 90H to I/O8 ID Read (2) Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 91H to I/ CEA t t ALH ALEA t REAID t REAID 00 98H Address Maker code input CEA t t ALH ALEA t REAID 00 20H Address input TC58DVM92A1FT00 76H Device code : 2003-01-10 19/44 ...
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... Ready/Busy: The output signal is used to indicate the operating condition of the device. The Busy state ( during the Program, Erase and Read operations and will return to Ready state ( after completion of the operation. The output buffer for this signal is an open drain. TC58DVM92A1FT00 GND ...
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... A1 A0 A14 A13 A12 A11 A10 A9 A22 A21 A20 A19 A18 A17 * A25 CLE ALE TC58DVM92A1FT00 32 pages (16K 512) bytes 32 pages 4096 blocks Column address A9 to A25 : Page address A14 to A25 : Block address A9 to A13 : NAND address in block 0V/Vcc 2003-01-10 21/44 ...
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... Table 4. Read mode operation states CLE ALE Output Select L Output Deselect L Standby Second Cycle Acceptable while Busy TC58DVM92A1FT00 HEX data bit assignment (Example) Serial Data Input: 80H I/ I/O1 I/O1 to I/O8 Power Output Active High impedance Active High impedance Standby 2003-01-10 22/44 ...
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... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page starts Cell array from column address 0. TC58DVM92A1FT00 2003-01-10 23/44 ...
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... A4-to-A7 address. (A “00H” command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output Busy Busy (01H) 256 527 A Sequential Read (2) TC58DVM92A1FT00 Data output t R Busy (50H) 512 527 A Sequential Read (3) 2003-01-10 24/44 ...
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... Status Read function can be used to determine the status of each individual device. OUTPUT Fail: 1 Busy: 0 Not Protected Device 3 Busy 70H Status on Device N BY pin signals from multiple devices are wired together as shown in the TC58DVM92A1FT00 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device 2003-01-10 25/44 ...
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... Verify operations Block Address Erase Start input: 3 cycles command TC58DVM92A1FT00 70 Status Read command automatically returns to Ready after completion of the operation. The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10H” command. ...
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... Dummy Program Dummy Dummy Data input Program Program command command command Data input Address Data input 0 to 527 input 0 to 527 (District 1) (District 2) TC58DVM92A1FT00 Multi block Data input Program command command 80 15 Address Data input input 0 to 527 80 15 (District 3) 2003-01-10 27/44 ...
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... Pass: 0 Fail: 1 District 0 area, it shows “Fail” condition. Do not care I/O3, I/O4 and I/O5 are as same manner Ready: 1 Busy I/O2. Protect: 0 Not Protect: 1 TC58DVM92A1FT00 byte) page write operation byte) page write operation in 2003-01-10 28/44 ...
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... Untill the Ready condition after the programming terminated by “10H” command, effective bit in the Status data is limited on Ready/Busy bit. In other words, Pass/Fail condition can be checked only in the Ready condition after “10H” command. TC58DVM92A1FT00 ···.., Block 4092 ···.., Block 4093 · ...
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... Pass: 0 Fail: 1 I/O2 describes Pass/Fail condition. Pass: 0 Fail fail occurred in District 0 area, it shows “Fail” condition. Pass: 0 Fail not care I/O3, I/O4 and I/O5 are as same manner as I/O2. Ready: 1 Busy: 0 Protect: 0 Not Protect: 1 TC58DVM92A1FT00 2003-01-10 30/44 ...
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... Example 1 : (60) [District 2] (60) [District 0] (60) [District 1] (D0) Example 2 : (60) [District 0] (60) [District 1] (60) [District 2] (60) [District 3] (D0) It requires no mutual address relation between the selected blocks from each District. TC58DVM92A1FT00 ···.., Block 4092 ···.., Block 4093 ···.., Block 4094 · ...
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... The second FF t (max 10 s) RST FF t RST FF t (max 6 s) RST command is invalid, but the third TC58DVM92A1FT00 Figure 8. 00 Figure 9. 00 (max 500 s) Figure 10. 00 Figure 11. I/O status: Pass/Fail Pass Ready/Busy Ready I/O status: Ready/Busy Busy Figure 12. (2) (3) FF ...
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... Table 6. ID Codes read out by ID read command (1) 90H I/O8 I/O7 Maker code 1 0 Device code CEA t ALEA t REAID 98H Maker code , t and t refer to the AC Characteristics. REAID CEA ALEA Figure 13. ID Read timing I/O6 I/O5 I/O4 I/O3 I/ TC58DVM92A1FT00 76H Device code I/O1 Hex Data 0 98H 0 76H 2003-01-10 33/44 ...
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... For the specifications of the access times t Table 7. ID Codes read out by command 91H I/O8 I/O7 Extended ID code CEA t ALEA t REAID 20H Extended ID code , t and t refer to the AC Characteristics. REAID CEA ALEA Figure 14. ID Read timing I/O6 I/O5 I/O4 I/O3 I/ TC58DVM92A1FT00 I/O1 Hex Data 0 20H 2003-01-10 34/44 ...
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... V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. For this operation the “FFH” command is needed. TC58DVM92A1FT00 Don’t care V IL 2003-01-10 35/44 ...
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... Read mode. In this case, data output starts automatically from address N and address input is unnecessary Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 Page 1 Page 2 Page 15 Page 31 Figure 17. page programming within a block 70 Status Read command input Figure 18. TC58DVM92A1FT00 Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2003-01-10 36/44 ...
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... C area Add Start point A area 10H Add DIN Start point C Area 10H Add DIN Start point B Area Figure 20. Example of How to Set the Pointer TC58DVM92A1FT00 255 256 511 512 527 B C Pointer control 50H Add Start point C area 00H Add Start point ...
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... V CC Device V SS Figure 21. This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value Ready 1.0 V Busy TC58DVM92A1FT00 / BY buffer consists of an open drain 3 25° 100 2003-01-10 38/44 ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE 80 DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min) WW TC58DVM92A1FT00 2003-01-10 39/44 ...
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... Although the device may read in a fifth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H or 50H Program operation CLE CE WE ALE I/O 80H Address input WE Internal read operation starts when WE goes High in the fourth cycle. Figure 22. Address input ignored Figure 23. TC58DVM92A1FT00 ignored Data input 2003-01-10 40/44 ...
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... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s All 1s Data Pattern 2 Figure 24. Address input Figure 25. TC58DVM92A1FT00 Data Pattern 3 Data Pattern 3 2003-01-10 41/44 ...
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... Valid (Good) Block Number 4016 Read Check: to verify the column address of Start Block No 1 Fail Read Check Pass Bad Block * 1 Block No. 4096 Yes End Figure 27 TC58DVM92A1FT00 TYP. MAX UNIT 4096 Block 517bytes of the first page in the block with FF (Hex) 2003-01-10 42/44 ...
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... Retry (2) ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. TC58DVM92A1FT00 2003-01-10 43/44 ...
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... Package Dimensions TC58DVM92A1FT00 2003-01-10 44/44 ...