TE28F640J3C115SL7HA Intel, TE28F640J3C115SL7HA Datasheet - Page 42

• Manufacturer Part Number: TE28F640J3C115SL7HA
• Description: IC FLASH 64MBIT 115NS 56TSOP
• Manufacturer: Intel

Specifications of TE28F640J3C115SL7HA

• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 860794

256-Mbit J3 (x8/x16)
11.0
11.1
11.2
42
Programming Operations
The device supports two different programming methods: word programming, and write-buffer
programming. Successful programming requires the addressed block to be unlocked. An attempt to
program a locked block will result in the operation aborting, and SR.1 and SR.4 being set,
indicating a programming error. The following sections describe device programming in detail.
Byte/Word Program
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup
(standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address
and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program
and program verify algorithms internally. After the program sequence is written, the device
automatically outputs SRD when read (see
page
SR.7.
When program is complete, SR.4 should be checked. If a program error is detected, the Status
Register should be cleared. The internal WSM verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in Read Status Register mode until it receives
another command.
Reliable byte/word programming can only occur when V
program is attempted while V
programs require that the corresponding block lock-bit be cleared. If a byte/word program is
attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.
Write to Buffer
To program the flash device, a Write to Buffer command sequence is initiated. A variable number
of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the
Write to Buffer Setup command is issued along with the Block Address (see
Buffer Flowchart” on page
information is loaded and XSR.7 reverts to “buffer available” status. If XSR.7 = 0, the write buffer
is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup
command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is
ready for loading.
Next, a word/byte count is given to the part with the Block Address. On the next write, a device
start address is given along with the write buffer data. Subsequent writes provide additional device
addresses and data, depending on the count. All subsequent addresses must lie within the start
address plus the count.
Internally, this device programs many flash cells in parallel. Because of this parallel programming,
maximum programming performance and lower power are obtained by aligning the start address at
the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0).
61). The CPU can detect the completion of the program event by analyzing the STS signal or
59). At this point, the eXtended Status Register (XSR, see
PEN
≤ V
PENLK
Figure 20, “Byte/Word Program Flowchart” on
, SR.4 and SR.3 will be set. Successful byte/word
CC
and V
PEN
are valid. If a byte/word
Figure 18, “Write to
Table
Datasheet
19)