MD4811-D512-V3Q18-X/Y SanDisk, MD4811-D512-V3Q18-X/Y Datasheet
MD4811-D512-V3Q18-X/Y
Specifications of MD4811-D512-V3Q18-X/Y
Related parts for MD4811-D512-V3Q18-X/Y
MD4811-D512-V3Q18-X/Y Summary of contents
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... Toshiba’s 0.13 µm Multi-Level Cell (MLC) NAND flash technology and x2 technology from M-Systems. MLC NAND flash technology provides the smallest die size by storing 2 bits of information in a single memory cell. x2 technology enables MLC NAND to achieve highly reliable, high-performance data and code storage with a specially designed error ...
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Performance MultiBurst read: 80 MB/sec Erase: 30 MB/sec Sustained read: 5 MB/sec Sustained write: 1.1 MB/sec Access time: Normal: 55 nsec Turbo: 33 nsec MultiBurst: 25 nsec Protection & Security-Enabling Features 16-byte Unique Identification (UID) number 6KByte user-controlled One Time ...
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TrueFFS Software Full hard-disk read/write emulation for transparent file system management Patented TrueFFS Flash file system management Automatic block management Data management to maximize the limit of typical flash life expectancy Dynamic virtual mapping Dynamic and static wear-leveling Programming, ...
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R H EVISION ISTORY Revision Date 1.1 September 2003 1 Description Updated RSRVD signal description DiskOnChip Control Register/Control Confirmation Register mapping corrected Icc – Active supply current updated Mechanical dimensions for 7x10 FBGA package updated 69-ball FBGA 9x12 daisy-chain ordering ...
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T C ABLE OF ONTENTS 1. Introduction ............................................................................................................................... 6 2. Product Overview ...................................................................................................................... 7 2.1 Product Description ............................................................................................................ 7 2.2 512Mb Standard Interface .................................................................................................. 8 2.2.1 Pin/Ball Diagrams................................................................................................................. 8 2.2.2 System Interface ................................................................................................................ 10 2.2.3 Signal Description .............................................................................................................. 11 2.3 ...
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... Wear-Leveling .................................................................................................................... 47 6.4.7 Power Failure Management ............................................................................................... 48 6.4.8 Error Detection/Correction.................................................................................................. 49 6.4.9 Special Features Through I/O Control (IOCTL) Mechanism.............................................. 49 6.4.10 Compatibility ....................................................................................................................... 49 6.5 8KB Memory Window ....................................................................................................... 49 7. Register Descriptions ............................................................................................................. 51 7.1 Definition of Terms ........................................................................................................... 51 7.2 Reset Values .................................................................................................................... 51 7.3 No Operation (NOP) Register........................................................................................... 52 7.4 Chip Identification (ID) Register [0:1]................................................................................ 52 7 ...
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DiskOnChip Control Register/Control Confirmation Register ........................................... 55 7.9 Device ID Select Register................................................................................................. 56 7.10 Configuration Register...................................................................................................... 56 7.11 Interrupt Control Register ................................................................................................. 57 7.12 Interrupt Status Register................................................................................................... 58 7.13 Output Control Register.................................................................................................... 59 7.14 DPD Control Register ....................................................................................................... 60 ...
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Product Specifications ........................................................................................................... 77 10.1 Environmental Specifications ........................................................................................... 77 10.1.1 Operating Temperature ...................................................................................................... 77 10.1.2 Thermal Characteristics ..................................................................................................... 77 10.1.3 Humidity.............................................................................................................................. 77 10.1.4 Endurance .......................................................................................................................... 77 10.2 Electrical Specifications.................................................................................................... 77 10.2.1 Absolute Maximum Ratings................................................................................................ 77 10.2.2 Capacitance........................................................................................................................ 78 10.2.3 ...
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... Section 4: Major features and benefits of x2 technology Section 5: Detailed description of hardware protection and security-enabling features Detailed description of modes of operation and TrueFFS technology, Section 6: including power failure management and 8KByte memory window Mobile DiskOnChip G3 register descriptions Section 7: Overview of how to boot from Mobile DiskOnChip G3 ...
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... Mobile DiskOnChip G3 512Mb has a 2KB Programmable Boot Block (4KB for Mobile DiskOnChip G3 1Gb). This block provides eXecute In Place (XIP) functionality, enabling Mobile DiskOnChip G3 to replace the boot device and function as the only non-volatile memory device on- board. Eliminating the need for an additional boot device reduces hardware expenditures, board real estate, programming time, and logistics. M-Systems’ ...
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Standard Interface 2.2.1 Pin/Ball Diagrams See Figure 1 and Figure 2 for the Mobile DiskOnChip G3 512Mb pinout/ballout for the standard interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not ...
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FBGA Package A0/ G VSS DPD H CE# OE# J RSRVD ...
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System Interface See Figure 3 for a simplified I/O diagram for a standard interface of Mobile DiskOnChip G3 512Mb. CE#, O E#, WE# Host System Bus System Interface Figure 3: Standard Interface Simplified I/O Diagram (Mobile DiskOnChip G3 512Mb) ...
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... ST Output Enable, active low Configuration ST Identification. Configuration control to support up to four chips cascaded in the same memory window. Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used for single-chip configuration Chip 2 = ID1, ID0 = VSS, VCCQ (0,1) Chip 3 = ID1, ID0 = VCCQ, VSS (1,0) Chip 4 = ID1, ID0 = VCCQ, VCCQ (1,1) ST Lock, active low ...
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Signal Pin No. DMARQ# 21 IRQ# 47 DPD 19 VCC 12 VCCQ 37 VSS 13, 25, 36, 48 RSRVD 20 The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...
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... Output Enable, active low Configuration ST Identification. Configuration control to support up to four chips cascaded in the same memory window. Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used for single chip configuration Chip 2 = ID1, ID0 = VSS, VCCQ (0,1) Chip 3 = ID1, ID0 = VCCQ, VSS (1,0) ...
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Signal Ball No. IRQ# F8 DPD G1 VCC J4 VCCQ J5 VSS G2, J8 RSRVD E3 See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain ...
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Standard Interface 2.3.1 Ball Diagram See Figure 4 for the Mobile DiskOnChip G3 1Gb standard interface ballout. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should not be connected. Note: Mobile DiskOnChip ...
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System Interface See Figure 5 for a simplified I/O diagram for a standard interface of Mobile DiskOnChip G3 1Gb. CE#, O E#, WE# Host System Bus System Interface Figure 5: Standard Interface Simplified I/O Diagram (Mobile DiskOnChip G3 1Gb) ...
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... Output Enable, active low. ST Configuration ST Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used for single chip configuration Chip 2 = ID1, ID0 = VCCQ, VCCQ (1,1) ST Lock, active low. When active, provides full hardware data protection of selected partitions ...
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Signal Ball No. IRQ# F9 DPD G2 VCC J5 VCCQ J6 VSS G3 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain ...
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Multiplexed Interface 2.4.1 Pin/Ball Diagram See Figure 6 and Figure 7 for the Mobile DiskOnChip G3 512Mb pinout/ballout for the multiplexed interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not ...
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FBGA Package VSS D VSS VSS E VSS VSS F VSS VSS G DPD VSS H CE# OE# J RSRVD AD0 K AD8 ...
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System Interface See Figure 8 for a simplified I/O diagram. Host System Bus Figure 8: Multiplexed Interface Simplified I/O Diagram 21 CE#, OE#, WE# Mobile DiskOnChip G3 AD[15:0] ID0 AVD# LOCK# System Interface Configuration Preliminary Data Sheet, Rev. 1.1 ...
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... DPD 19 ST Deep Power-Down. Used to enter and exit Deep Power-Down 22 Description System Interface Configuration cascaded in the same memory window. Chip 1 = ID0 = VSS; must be used for single-chip configuration Chip 2 = ID0 = VCCQ protection of selected partitions. Control initializing and should not be accessed KΩ pull-up resistor is required if this pin drives an input. ...
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Input Signal Pin No. Type VCCQ 37,22 - VCC 12 - VSS 5-11, 14-18, - 13, 25, 36, 48 RSRVD 20 - The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open ...
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... Output Enable, active low Configuration ST Set multiplexed interface ST Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1 = ID0 = VSS; must be used for single-chip configuration Chip 2 = ID0 = VCC ST Lock, active low. When active, provides full hardware data protection of selected partitions. ...
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Signal Ball No. VCC J4 VCCQ J5, F3 VSS G2,J8, D7,C7,F6,E6, C6,C2,D2,E2, F2,D1,E1,F1 Reserved See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output 25 ...
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Multiplexed Interface 2.5.1 Ball Diagram See Figure 9 for the Mobile DiskOnChip G3 1Gb (dual-die) ball diagram. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should not be connected. Note: Mobile DiskOnChip ...
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System Interface See Figure 10 for a simplified I/O diagram. Host System Bus Figure 10: Multiplexed Interface Simplified I/O Diagram 27 CE#, OE#, WE# Mobile DiskOnChip G3 1Gb AD[15:0] LOCK# ID0 AVD# System Interface Configuration Preliminary Data Sheet, Rev. ...
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Signal Description 9x12 FBGA Package Table 6: Signal Descriptions for Multiplexed Interface (Mobile DiskOnChip G3 1Gb 9x12 FBGA Package) Input Signal Ball No. Type AD[15:14] H8 Multiplexed bus. AD[13:12] H7, J7 AD[11:9] K5, J4, H4 AD[8:6] K3, ...
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Input Signal Ball No. Type VCC J5 - VCCQ J6 VSS G3,J9, - D8,C8,F7,E7, C7,C3,D3,E3 ,F3,D2,E2,F2 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger ...
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T O HEORY OF PERATION 3.1 Overview Mobile DiskOnChip G3 consists of the following major functional blocks, as shown in Figure 11. *ADDR[0] and DPD are multiplexed on the same ball/pin. Figure 11: Mobile DiskOnChip G3 Simplified Block Diagram, ...
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... Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system initialization. A 13-bit wide address bus enables access to the Mobile DiskOnChip G3 8KB memory window (as shown in Section 6.5). A 16-bit internal data bus is supported by parallel access to two 256Mb flash planes (for 512Mb single-die devices), each of which enables 8-bit access. This 16-bit data bus permits 16-bit wide access to the host ...
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... Mobile DiskOnChip G3. 3.4.1 Read/Write Protection Data and code protection is implemented through a Protection State Machine (PSM). The user can configure one or two independently programmable areas of the flash memory as read protected, write protected, or read/write protected. A protected partition may be protected by either/both of these hardware mechanisms: • ...
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Unique Identification (UID) Number Each Mobile DiskOnChip G3 is assigned a 16-byte UID number. Burned onto the flash during production, the UID cannot be altered and is unique worldwide. The UID is essential in security- related applications, and can ...
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The Programmable Boot Block size available for Mobile DiskOnChip G3 1Gb (dual-die KB. 3.6 Download Engine (DE) Upon power-up or when the RSTIN# signal is asserted, the DE automatically downloads the Initial Program Loader (IPL) to the ...
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Control and Status The Control and Status block contains registers responsible for transferring address, data and control information between the DiskOnChip TrueFFS driver and the flash media. Additional registers are used to monitor the status of the flash media ...
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Bad units are mapped individually on each plane by enabling unaligned unit access, as shown in Figure 14. Good units ...
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T X ECHNOLOGY Mobile DiskOnChip G3 enhances performance using various proprietary techniques: • Parallel access to the separate 256Mb flash planes, thereby providing an internal 32-bit data bus. See Section 3.10 for further information. • MultiBurst operation to ...
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Host Internal data transfers /Flash_OE Data transfer from Flash Planes to FIFO External data transfers /DiskOnChip_OE Data transfer from FIFO to Host Note: Mobile DiskOnChip G3 does not support MultiBurst write operations. MultiBurst operation is controlled by 5 ...
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The LATENCY bit is the third bit that must be set in the MultiBurst Mode Control register. When the LATENCY bit is set to 0, the host can latch the first 16-bit data word two clock cycles after CLK0. This ...
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Set the bits in the Interrupt Control register (see Section 7) to enable interrupts on an ECC error and at the end of the DMA operation. 3. Write to the DMA Control register[0] to set the DMA_EN bit, the ...
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H P ARDWARE ROTECTION 5.1 Method of Operation Mobile DiskOnChip G3 enables the user to define two partitions that are protected (in hardware) against any combination of read or write operations. The two protected areas can be configured as ...
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Low-Level Structure of the Protected Area The first five blocks in Mobile DiskOnChip G3 contain foundry information, the Data Protect structures, IPL code, and bad block mapping information. See Figure 16. Bad Block Table and Factory-Programmed UID Data Protect ...
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Block 3 and 4 o Data Protect Structure 1. This structure contains configuration information on one of the two user-defined protected partitions. o IPL Code (2KB). This is the boot code that is downloaded by the DE to the internal ...
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M O ODES OF PERATION Mobile DiskOnChip G3 operates in one of three basic modes: • Normal mode • Reset mode • Deep Power-Down mode The current mode of the chip can always be determined by reading the DiskOnChip ...
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... Normal Mode This is the mode in which standard operations involving the flash memory are performed. Normal mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control Confirmation register. The boot detector circuit triggers the software to set the device to Normal mode ...
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... TrueFFS Technology 6.4.1 General Description M-Systems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk, making it completely transparent to the OS. In addition, since it operates under the OS file system layer (see Figure 18 completely transparent to the application ...
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... Wear-Leveling Flash memory can be erased a limited number of times. This number is called the erase cycle limit, or write endurance limit, and is defined by the flash array vendor. The erase cycle limit applies to each individual erase block in the flash device. In Mobile DiskOnChip G3, the erase cycle limit of the flash is 100,000 erase cycles ...
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... If wear-leveling were only applied on newly written pages, static areas would never be cycled. This limited application of wear-leveling would lower life expectancy significantly in cases where flash memory contains large static areas. To overcome this problem, TrueFFS forces data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media ...
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... The 2KB Programmable Boot Block is in section 0 and section 3, to support systems that search for a checksum at the boot stage both from the top and bottom of memory. The addresses described here are relative to the absolute starting address of the 8KB memory window. ...
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... Figure 19: Mobile DiskOnChip G3 Memory Map 50 Reset Mode Normal Mode 000H Programmable Programmable Boot Block Boot Block Section 0 800H Flash area 00H Section 1 (+ aliases) 00H Section 2 Registers Programmable Programmable Boot Block Boot Block Section 3 Preliminary Data Sheet, Rev. 1.1 Mobile DiskOnChip G3 ...
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R D EGISTER ESCRIPTIONS This section describes various Mobile DiskOnChip G3 registers and their functions, as listed in Table 7. Most Mobile DiskOnChip G3 registers are 8-bit, unless otherwise denoted as 16-bit. Address (Hex) 103E 1000/1074 1004 1006 1008 ...
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... Chip Identification Register[1]: FDFFH 7.5 Test Register Description: This register enables software to identify multiple Mobile DiskOnChip G3 devices or multiple aliases in the CPUs memory space. Data written is stored but does not affect the behavior of Mobile DiskOnChip G3. Address (hex): 1004 Type: Read/Write Reset Value: 0 Bit No ...
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Bus Lock Register Description: This register provides a mechanism for a CPU to request and hold sole access rights to Mobile DiskOnChip G3 in multiprocessor applications. The following algorithm must be implemented to ensure that only one CPU at ...
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Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the byte swap ...
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... DiskOnChip Control register, the complement of that data byte must also be written to the Control Confirmation register. The two writes cycles must not be separated by any other read or write cycles to the Mobile DiskOnChip G3 memory space, except for reads from the Programmable Boot Block space. Address 100C/1072 ...
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Device ID Select Register Description cascaded configuration, this register controls which device provides the register space. The value of bits ID[0:1] is compared to the value of the ID configuration input pins/balls. The device whose ID input ...
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Interrupt Control Register Description: This 16-bit register controls how interrupts are generated by Mobile DiskOnChip G3, and indicates which of the following five sources has asserted an interrupt: 0: Flash array is ready 1: Data protection violation 2: Reading ...
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Bit No. 14 EDGE. Selects edge or level triggered interrupts: 0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the interrupt is cleared. 1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low and return to ...
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Output Control Register Description: This register controls the behavior of certain output signals. This register is reset by a hardware reset, not by entering Reset mode. Note: When multiple devices are cascaded, writing to this register will affect all ...
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DPD Control Register Description: This register specifies the behavior of the DPD input signal. Address (hex): 107C Bit 7 Bit 6 Read/Write Description PD_OK Reset Value 0 Bit No. 3-0 MODE[0:3]. Controls the behavior of the DPD input: 0000: ...
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DMA Control Register [1:0] Description: These two 16-bit registers specify the behavior of the DMA operation. Address (hex): 1078/107A Bit 7 Bit 6 Read/Write R Description RFU_0 Reset Value 0 Bit 15 Bit 14 Read/Write R Description DMA_EN PAUSE ...
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Read/Write Description Reset Value 0 Bit No. 9-0 NEGATE_COUNT. When the EDGE bit of the DMA Control register[ this bit must be programmed to specify the bus cycle in which DMARQ# will be negated, as follows: NEGATE_COUNT = ...
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MultiBurst Mode Control Register Description: This 16-bit register controls the behavior of Mobile DiskOnChip G3 during MultiBurst mode read cycles. Address (hex): 101C Bit 7 Bit 6 Read/Write Description Reset Value 0 Bit 15 Bit 14 Read/Write Description Reset ...
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... ROM devices. When Mobile DiskOnChip G3 is located, the BIOS code executes from it the IPL code, located in the XIP portion of the Programmable Boot Block. This code loads the TrueFFS driver into system memory, installs Mobile DiskOnChip disk in the system, and then returns control to the BIOS code. The operating system subsequently identifies Mobile DiskOnChip available disk ...
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Mobile DiskOnChip G3 can be used as the only disk in the system, with or without a floppy drive, and with or without hard disks. The drive letter assigned depends on how Mobile DiskOnChip G3 is ...
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Non-PC Architectures In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually loaded from the storage device. When using Mobile DiskOnChip G3 as the system boot device, the CPU fetches the first ...
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... ESIGN ONSIDERATIONS 9.1 General Guidelines A typical RISC processor memory architecture is shown in Figure 21. It may include the following devices: • Mobile DiskOnChip G3: Contains the OS image, applications, registry entries, back-up data, user files and data, etc. It can also be used to perform boot operation, thereby replacing the need for a separate boot device. • ...
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... With a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), as shown in Figure 22 below. Typically, Mobile DiskOnChip G3 can be mapped to any free 8KB memory space PC-compatible platform usually mapped into the BIOS expansion area. If the allocated memory window is larger than 8KB, an automatic anti-aliasing mechanism prevents the firmware from being loaded more than once during the ROM expansion search ...
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... Chip Enable (CE#) – Connect this signal to the memory address decoder. Most RISC processors include a programmable decoder to generate various Chip Select (CS) outputs for different memory zones. These CS signals can be programmed to support different wait states to accommodate Mobile DiskOnChip G3 timing specifications. • Power-On Reset In (RSTIN#) – Connect this signal to the host active-low Power-On Reset signal ...
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Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 22. Both signals must be connected to VSS if the host uses only one DiskOnChip. If more than one device is being used, refer to Section 9.6 for ...
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Implementing the Interrupt Mechanism 9.5.1 Hardware Configuration To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to the host interrupt input. Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball. ...
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Device Cascading When connecting Mobile DiskOnChip G3 512Mb using a standard interface four devices can be cascaded with no external decoding circuitry. Figure 24 illustrates the configuration required to cascade four devices on the host bus (only ...
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Boot Replacement A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also required to access Mobile DiskOnChip G3 during the boot sequence in order to load OS images and the device drivers. M-Systems’ ...
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Platform-Specific Issues This section discusses hardware design issues for major embedded RISC processor families. 9.8.1 Wait State Wait states can be implemented only when Mobile DiskOnChip G3 is designed in a bus that supports a Wait state insertion, and ...
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Data Access Mode When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even address accesses to the ...
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Design Environment Mobile DiskOnChip G3 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and development with Mobile DiskOnChip G3, even before the target platform is available. • Programming solutions: o GANG programmer ...
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P S RODUCT PECIFICATIONS 10.1 Environmental Specifications 10.1.1 Operating Temperature Commercial temperature range: Extended temperature range: -40°C to +85°C 10.1.2 Thermal Characteristics Junction to Case (θ 10.1.3 Humidity 10% to 90% relative, non-condensing 10.1.4 Endurance Mobile DiskOnChip G3 is ...
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Capacitance Symbol Parameter Input capacitance (512Mb device Input capacitance (1Gb device) Output capacitance (512Mb device) C OUT Output capacitance (1Gb device) Capacitance is not 100% tested. 10.2.3 DC Electrical Characteristics over Operating Range See Table 12 and ...
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Table 13: DC Characteristics, VCCQ = 2.5V-3.6V Symbol Parameter VCC Core supply voltage VCCQ Input/Output supply voltage V High-level input voltage IH V Low-level input voltage IL Maximum high level output I OHmax current Maximum low-level output I OLmax current ...
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AC Operating Conditions Timing specifications are based on the conditions defined below. Parameter Ambient temperature (TA) Core supply voltage (VCC) Input pulse levels Input rise and fall times Input timing levels Output timing levels Output load 80 Table 14: ...
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Timing Specifications 10.3.1 Read Cycle Timing Standard Interface t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 27: Standard Interface, Read Cycle Timing t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 28: Standard Interface ...
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Table 15: Standard Interface Read Cycle Timing Parameters Symbol Description Tsu(A) Address to OE# Tho(A) OE# to Address hold time Tsu(CE0) CE# to OE# setup time Tho(CE0) OE# to CE# hold time Tho(CE1) OE# or WE# to CE# Tsu(CE1) CE# ...
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Write Cycle Timing Standard Interface t SU A[12:0] t (CE1) HO CE# OE# WE# D[15:0] Figure 29: Standard Interface Write Cycle Timing Table 16: Standard Interface Write Cycle Parameters Symbol Description T (A) Address to WE# SU Tho(A) WE# ...
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Read Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] CE# t (CE1) HO OE# WE# Figure 30: Multiplexed Interface Read Cycle Timing Table 17: Multiplexed Interface Read Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...
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Write Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] t (CE1) HO CE# OE# WE# Figure 31: Multiplexed Interface Write Cycle Timing Table 18: Multiplexed Interface Write Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...
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Read Cycle Timing MultiBurst In Figure 32, the MultiBurst Control register values are: LATENCY=0, LENGTH=4, CLK_INV=0. t (CLK1) W CLK t (OE0-CLK0) HO OE# t (OE0-CLK1 (OE0-CLK1) SU D[15:0] (HOLD=0) D[15:0] (HOLD=1) Insert LATENCY clock cycles Note: ...
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... Power-Up Timing Mobile DiskOnChip G3 is reset by assertion of the RSTIN# input. When this signal is negated, Mobile DiskOnChip G3 initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this procedure, Mobile DiskOnChip G3 does not respond to read or write accesses. ...
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VCC = 2.5V VCCQ = 1.65 or 2.5V VCC RSTIN# BUSY# A[12:0] CE#, OE# (WE (Read cycle) AVD# (Muxed Mode Only) DPD (A[0]) Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width ...
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Interrupt Timing IRQ# Symbol Tw(IRQ#) IRQ# asserted pulse width (Edge mode) 10.3.9 DMA Request Timing OE#/CE# DMARQ# Note: Polarity of DMARQ# may be inverted based on the NORMAL bit of DMA Control Register[0]. Symbol Tw(DMARQ#) DMARQ# asserted pulse width ...
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Mechanical Dimensions 10.4.1 Mobile DiskOnChip G3 512Mb TSOP-I dimensions: 20.0±0. 12.0±0. 1.1±0.10 mm Figure 36: Mechanical Dimensions TSOP-I Package 90 Preliminary Data Sheet, Rev. 1.1 Mobile DiskOnChip G3 91-SR-011-05-8L ...
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FBGA dimensions: 7.0±0. 10.0±0. 1.1±0.1 mm Ball pitch: 0.8 mm Figure 37: Mechanical Dimensions 7x10 FBGA Package 91 Preliminary Data Sheet, Rev. 1.1 Mobile DiskOnChip G3 91-SR-011-05-8L ...
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Mobile DiskOnChip G3 1Gb (Dual-Die) FBGA dimensions: 9.0±0. 12.0±0. 1.3±0.1 mm Ball pitch: 0.8 mm 9.0 12.0 Figure 38: Mechanical Dimensions 9x12 FBGA Package 92 1.2/ 0.90 1.4(max) 0.33±0. 0.47±0.05 ...
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... Refer to Table 23 for combinations currently available and the associated order numbers. Ordering Code MD4811-d512-V3Q18 MD4811-d512-V3Q18-X MD4811-d512-V3Q18-P MD4811-d512-V3Q18-X-P MD4832-d512-V3Q18-X MD4832-d512-V3Q18-X-P MD4331-d1G-V3Q18-X MD4331-d1G-V3Q18-X-P MD4331-d00-DAISY MD4832-d00-DAISY MD4811-d512-MECH MD4832-d512-MECH MD4331-d1G-MECH 93 MDxxxx-Dxxx-xxx-T-C Capacity D- MByte d- Mbit xxx - Value Supply Voltage V3Q18 - 3.3V core, 1.8V I/O Figure 39: Ordering Information Structure ...
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ONTACT S USA M-Systems Inc. 8371 Central Ave, Suite A Newark CA 94560 Phone: +1-510-494-2090 Fax: +1-510-494-5545 Japan M-Systems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: +81-3-5423-8102 ...